Abstract: The present invention relates to a method of testing of digital and analog circuits. If a fault is detected, after stimuli are applied and test measurements are made at some circuit nodes, steps are taken to locate faulty circuit components. At least one further node is selected for measurement on the basis of the levels of information that such nodes can provide. Further measurements aid fault location.For analog circuits, levels of information are determined by calculation of discrimination factors which depend on possible voltage ranges at unmeasured circuit nodes if various components are considered as faulty. The information gained from measurement at a further node is used to reduce the voltage ranges in order to aid selection of another node to measure.

Abstract: An analogue circuit or unit under test is tested utilizing automatic test equipment and an interface unit to apply stimuli to the circuit the stimuli including supply potentials. A computer analyses the circuit as a network of nodes and modules to deduce a set of ranges of values at selected nodes, the ranges being determined from the set of the stimuli and a resultant set of test measurements, taken from nodes of the circuit by the interface and automatic test equipment, taking into account tolerances in the stimuli, the measurements and the nominal parameters of components of the circuit. If there is inconsistency among the derived ranges the computer treats as potentially faulty any module which could remove the inconsistency if the constraints imposed by that module were suspended.