Abstract: The verification process is applied to a programme (4) when it is being integrated into an electronic device (2), the programme being organized on the basis of types linked by parentage relationships, each type being identified by a respective code. The invention is characterized in that it comprises a phase which consists in carrying out unification of the types so as to determine their nearest common ancestor using a form of said code including a pattern of bits in accordance with a formalism which expresses the parentage of the type with which it is associated, and by performing a logical combination of the patterns assigned to the types to be unified, producing the pattern of the type which is their nearest common ancestor. The invention enables verification in devices with limited storage memory resources, in particular smart cards (2).