Patents by Inventor Antti Iihola
Antti Iihola has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240343558Abstract: A device is provided that includes a handle layer with at least one cavity and suspension structure, a patterned polycrystalline silicon (poly-Si) first device layer, where at least one structural element is suspended by the structure, and may include a seismic element. A second electrically insulating layer is present, followed by a second device layer of patterned single-crystal silicon (mono-Si) with at least one moveably suspended seismic element above the first layer. A cap layer finalizes the structure, with the handle layer, device layers, and the cap layer forming an enclosure's walls. The first and second insulating layers bond the handle and device layers. The enclosure includes at least one seismic element from the second device layer, and at least one static and moveable electrode for motion detection or causation, with the static electrode in the first device layer.Type: ApplicationFiled: April 11, 2024Publication date: October 17, 2024Inventors: Petteri KILPINEN, Marko PEUSSA, Antti IIHOLA, Altti TORKKELI
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Patent number: 12043542Abstract: A microelectromechanical structure including a first wafer structure attached by bonding to a second wafer structure. The first wafer structure includes a build part of silicon wafer material, a through via, and an isolation structure separating the through via from the build part. The through via extends between a first electrical contact and a second electrical contact through the first wafer structure in a first direction. The first electrical contact of the first wafer structure is accessible externally and the second electrical contact of the first wafer structure connects to an internal electrical contact on the second wafer structure. In the first direction, the extent of the isolation structure includes a hollow section and a via fill section where the isolation structure is filled with solid electrically insulating material. enables considerable increase of gap height in MEMS structures.Type: GrantFiled: March 3, 2020Date of Patent: July 23, 2024Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Altti Torkkeli, Antti Iihola
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Publication number: 20240116753Abstract: A method is provided for sealing and contacting a microelectromechanical device that includes a silicon device wafer with MEMS device structures and a cap wafer with an electrical circuit. The device wafer includes a sealing region and an interconnection region. Moreover, the cap wafer includes a corresponding sealing region and an interconnection region. Layers of eutectic metal alloy material are deposited on the sealing and the interconnection regions of the device wafer and the cap wafer. The cap wafer is bonded to the device wafer so that the interconnection region of the device wafer is aligned with the interconnection region of the cap wafer and the sealing region of the device wafer is aligned with the sealing region of the cap wafer.Type: ApplicationFiled: October 10, 2023Publication date: April 11, 2024Inventors: Antti IIHOLA, Jeanette LINDROOS
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Patent number: 11792941Abstract: The present publication discloses a circuit-board structure, including a conductor layer on an insulating material layer, and a conductor pattern on top of the conductor foil. A component is attached to the conductor foil and the conductor pattern, the component embedded at least in part in adhesive which attaches the component to the insulating material layer. A recess is formed in the conductor foil and the insulating material layer, and contact openings are in the insulating material layer at locations of contact areas of the component. Conductor material of the conductor foil is not present outside the conductor pattern, and the conductor foil is located between the conductor pattern and the insulating material layer.Type: GrantFiled: August 30, 2021Date of Patent: October 17, 2023Assignee: IMBERATEK, LLCInventors: Risto Tuominen, Antti Iihola, Petteri Palm
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Patent number: 11716816Abstract: This publication discloses an electronic module, comprising a first conductive pattern layer and a first insulating-material layer on at least one surface of the first conductive pattern layer, at least one opening in the first insulating-material layer that extends through the first insulating-material layer, a component having a contact surface with contact terminals, the component being arranged at least partially within the opening with its contact terminals electrically coupled to the first conductive pattern layer, a second insulating-material layer provided on the first insulating-material layer, and a conductive pattern embedded between the first and second insulating material layers. This publication additionally discloses a method for manufacturing an electronic module.Type: GrantFiled: June 30, 2021Date of Patent: August 1, 2023Assignee: IMBERATEK, LLCInventors: Antti Iihola, Timo Jokela
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Publication number: 20210392752Abstract: The present publication discloses a method for manufacturing a circuit-board structure. In the method, a conductor layer is made, which comprises a conductor foil and a conductor pattern on the surface of the conductor foil. A component is attached to the conductor layer and the conductor layer is thinned, in such a way that the conductor material of the conductor layer is removed from outside the conductor pattern.Type: ApplicationFiled: August 30, 2021Publication date: December 16, 2021Inventors: Risto Tuominen, Antti Iihola, Petteri Palm
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Publication number: 20210329788Abstract: This publication discloses an electronic module, comprising a first conductive pattern layer and a first insulating-material layer on at least one surface of the first conductive pattern layer, at least one opening in the first insulating-material layer that extends through the first insulating-material layer, a component having a contact surface with contact terminals, the component being arranged at least partially within the opening with its contact terminals electrically coupled to the first conductive pattern layer, a second insulating-material layer provided on the first insulating-material layer, and a conductive pattern embedded between the first and second insulating material layers. This publication additionally discloses a method for manufacturing an electronic module.Type: ApplicationFiled: June 30, 2021Publication date: October 21, 2021Inventors: Antti Iihola, Timo Jokela
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Patent number: 11134572Abstract: The present publication discloses a method for manufacturing a circuit-board structure. In the method, a conductor layer is made, which comprises a conductor foil and a conductor pattern on the surface of the conductor foil. A component is attached to the conductor layer and the conductor layer is thinned, in such a way that the conductor material of the conductor layer is removed from outside the conductor pattern.Type: GrantFiled: November 18, 2016Date of Patent: September 28, 2021Assignee: IMBERATEK, LLCInventors: Risto Tuominen, Antti Iihola, Petteri Palm
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Patent number: 10798823Abstract: This publication discloses an electronic module, comprising a first conductive pattern layer and a first insulating-material layer on at least one surface of the first conductive pattern layer, at least one opening in the first insulating-material layer that extends through the first insulating-material layer, a component having a contact surface with contact terminals, the component being arranged at least partially within the opening with its contact terminals electrically coupled to the first conductive pattern layer, a second insulating-material layer provided on the first insulating-material layer, and a conductive pattern embedded between the first and second insulating material layers. This publication additionally discloses a method for manufacturing an electronic module.Type: GrantFiled: December 23, 2014Date of Patent: October 6, 2020Assignee: IMBERATEK, LLCInventors: Antti Iihola, Timo Jokela
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Publication number: 20200283292Abstract: A microelectromechanical structure including a first wafer structure attached by bonding to a second wafer structure. The first wafer structure includes a build part of silicon wafer material, a through via, and an isolation structure separating the through via from the build part. The through via extends between a first electrical contact and a second electrical contact through the first wafer structure in a first direction. The first electrical contact of the first wafer structure is accessible externally and the second electrical contact of the first wafer structure connects to an internal electrical contact on the second wafer structure. In the first direction, the extent of the isolation structure includes a hollow section and a via fill section where the isolation structure is filled with solid electrically insulating material. enables considerable increase of gap height in MEMS structures.Type: ApplicationFiled: March 3, 2020Publication date: September 10, 2020Inventors: Altti TORKKELI, Antti IIHOLA
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Publication number: 20200187358Abstract: This publication discloses an electronic module, comprising a first conductive pattern layer and a first insulating-material layer on at least one surface of the first conductive pattern layer, at least one opening in the first insulating-material layer that extends through the first insulating-material layer, a component having a contact surface with contact terminals, the component being arranged at least partially within the opening with its contact terminals electrically coupled to the first conductive pattern layer, a second insulating-material layer provided on the first insulating-material layer, and a conductive pattern embedded between the first and second insulating material layers. This publication additionally discloses a method for manufacturing an electronic module.Type: ApplicationFiled: February 12, 2020Publication date: June 11, 2020Inventors: Antti Iihola, Timo Jokela
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Patent number: 10231335Abstract: The present invention generally provides a novel method for manufacturing an electronic module with crossed conducting lines and a novel electronic module with crossed conducting lines. In particular, an aspect of the present invention is to provide a thin, single layer electronic module. It is also an object of the present invention to provide an electronic module with an embedded jumper element having reliable high quality connections and contacts. To achieve at least some of the aspects of the present invention, an embedded pre-fabricated jumper module is placed inside a printed circuit board which allows the crossing of conducting lines within the module without manufacturing additional layers over the whole PCB board. The resultant PCB will have improved contacts and will not have surface deformation.Type: GrantFiled: May 23, 2014Date of Patent: March 12, 2019Assignee: GE Embedded Electronics OyInventors: Petteri Palm, Tuomas Waris, Antti Iihola
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Patent number: 10085347Abstract: Method for the manufacture of a circuit board containing a component and circuit board containing a component. The invention is based on first manufacturing (101-102 or 101-103) an intermediate product, which contains the insulator layer of the circuit board and the components, which are set in place inside the insulator layer, in such a way that the contact elements of the components face the surface of the intermediate product. After this, the intermediate product is transferred to the circuit-board manufacturing line, on which a suitable number of conducting-pattern layers and, if necessary, insulator layers are manufactured (104) on one or both sides of the intermediate product, in such a way that, when manufacturing the first conducting-pattern layer, the conductor material forms an electrical contact with the contact elements of the components. Alternatively, stages (101-105) can also be performed on a single manufacturing line.Type: GrantFiled: March 18, 2015Date of Patent: September 25, 2018Assignee: GE Embedded Electronics OyInventors: Risto Tuominen, Petteri Palm, Antti Iihola
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Patent number: 9969615Abstract: A method for manufacturing a micromechanical device layer is performed on a device wafer comprising a single layer of homogenous material. The method comprises patterning a first mask on a first face of the device wafer, the first mask patterning at least lateral dimensions of comb structures and outlines of large device structures. First trenches are etched, the first trenches defining the lateral dimensions of the at least comb structures and outlines of large device structures in a single deep etching process. Recession etching may be used on one or two faces of the device wafer for creating structures at least partially recessed below the respective surfaces of the device wafer. A double mask etching process may be used on one or two faces of the device wafer for creating structures at least partially recessed to mutually varying depths from the respective face of the device wafer.Type: GrantFiled: May 5, 2016Date of Patent: May 15, 2018Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Antti Iihola, Altti Torkkeli
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Patent number: 9883587Abstract: Manufacturing method and circuit module, which comprises an insulator layer and, inside the insulator layer, at least one component, which comprises contact areas, the material of which contains a first metal. On the surface of the insulator layer are conductors, which comprise at least a first layer and a second layer, in such a way that at least the second layer contains a second metal. The circuit module comprises contact elements between the contact areas and the conductors for forming electrical contacts. The contact elements, for their part, comprise, on the surface of the material of the contact area, an intermediate layer, which contains a third metal, in such a way that the first, second, and third metals are different metals and the contact surface area (ACONT 1), between the intermediate layer and the contact area is less that the surface area (APAD) of the contact area.Type: GrantFiled: March 30, 2016Date of Patent: January 30, 2018Assignee: GE Embedded Electronics OyInventors: Petteri Palm, Risto Tuominen, Antti Iihola
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Patent number: 9820375Abstract: Rigid-flex-type circuit-board structure and manufacturing method, in which a flexible membrane and a sacrificial-material piece are attached to an insulator membrane in the location of the flexible zone. An insulator layer, which encloses within itself a sacrificial-material piece is manufactured on the surface of the conductor membrane. The flexible zone is formed in such a way that an opening is made in the insulator layer, through which the sacrificial-material piece is removed. The flexible zone comprises at least part of the flexible membrane as well as conductors, which are manufactured by patterning the insulator membrane at a suitable stage in the method.Type: GrantFiled: January 17, 2017Date of Patent: November 14, 2017Assignee: GE Embedded Electronics OyInventors: Antti Iihola, Tuomas Waris
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Publication number: 20170271288Abstract: Manufacturing method and a multi-chip package, which comprises a conductor pattern and insulation, and, inside the insulation, a first component, the contact terminals of which face towards the conductor pattern and are conductively connected to the conductor pattern. The multi-chip package also comprises inside the insulation a second semiconductor chip, the contact terminals of which face towards the same conductor pattern and are conductively connected through contact elements to this conductor pattern. The semiconductor chips are located in such a way that the first semiconductor chip is located between the second semiconductor chip and the conductor pattern.Type: ApplicationFiled: June 2, 2017Publication date: September 21, 2017Inventors: Antti Iihola, Risto Tuominen
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Patent number: 9764942Abstract: The present invention relates to a micromechanical device comprising a multi-layer micromechanical structure including only homogenous silicon material. The device layer comprises at least a rotor and at least two stators. At least some of the rotor and at least two stators are at least partially recessed to at least two different depths of recession from a first surface of the device layer and at least some of the rotor and at least two stators are at least partially recessed to at least two different depths of recession from a second surface of the device layer.Type: GrantFiled: May 5, 2016Date of Patent: September 19, 2017Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Antti Iihola, Altti Torkkeli, Ville-Pekka Rytkönen, Matti Liukku
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Patent number: 9691724Abstract: Manufacturing method and a multi-chip package, which comprises a conductor pattern and insulation, and, inside the insulation, a first component, the contact terminals of which face towards the conductor pattern and are conductively connected to the conductor pattern. The multi-chip package also comprises inside the insulation a second semiconductor chip, the contact terminals of which face towards the same conductor pattern and are conductively connected through contact elements to this conductor pattern. The semiconductor chips are located in such a way that the first semiconductor chip is located between the second semiconductor chip and the conductor pattern.Type: GrantFiled: January 23, 2014Date of Patent: June 27, 2017Assignee: GE Embedded Electronics OyInventors: Antti Iihola, Risto Tuominen
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Patent number: 9674948Abstract: Rigid-flex-type circuit-board structure and manufacturing method, in which a flexible membrane and a sacrificial-material piece are attached to an insulator membrane in the location of the flexible zone. An insulator layer, which encloses within itself a sacrificial-material piece is manufactured on the surface of the conductor membrane. The flexible zone is formed in such a way that an opening is made in the insulator layer, through which the sacrificial-material piece is removed. The flexible zone comprises at least part of the flexible membrane as well as conductors, which are manufactured by patterning the insulator membrane at a suitable stage in the method.Type: GrantFiled: July 15, 2016Date of Patent: June 6, 2017Assignee: GE Embedded Electronics OyInventors: Antti Iihola, Tuomas Waris