Abstract: An electronic circuit for a switching power amplifier is shown where in order to reduce problems during the transition stage when switching an output stage of the amplifier, the circuit comprises an output stage formed by at least two switching stages 54,55. Each of the switching stages 54,55 comprises at least two power switches and provides an output between the at least two power switches. Further, the switching stages 54,55 are connected in parallel to each other. The proposed circuit comprises in addition clocking means for switching the power switches, wherein the clocking means switch the power switches of at least one of the switching stages 55 in an overlapped mode and the power switches of at least one other of the switching stages 54 in a non-overlapped mode. The invention relates equally to a corresponding method.

Abstract: Disclosed is a method for calibrating a delay-locked loop containing a chain of delay line elements that propagate a reference clock from delay line element to delay line element. Also disclosed is a delay-locked loop that operates in accordance with the method. The method includes, during a calibration procedure, sequentially varying the configuration of the chain of delay line elements so that there is one unused delay line element and a plurality of used delay line elements and, for each configuration, electrically compensating at least one delay line element based on a phase comparison results obtained from previous calibration configurations of the delay line elements so as to set the total delay through the chain of delay line elements at a desired value. The phase comparison is made between the reference clock and the propagated reference clock.

Abstract: An electronic circuit for a switching power amplifier is shown where in order to reduce problems during the transition stage when switching an output stage of the amplifier, the circuit comprises an output stage formed by at least two switching stages 54,55. Each of the switching stages 54,55 comprises at least two power switches and provides an output between the at least two power switches. Further, the switching stages 54,55 are connected in parallel to each other. The proposed circuit comprises in addition clocking means for switching the power switches, wherein the clocking means switch the power switches of at least one of the switching stages 55 in an overlapped mode and the power switches of at least one other of the switching stages 54 in a non-overlapped mode. The invention relates equally to a corresponding method.

Abstract: The invention relates to a method and an apparatus for identifying a heartbeat. In the method, an arterial pressure signal is measured in the form of multichannel measurement, and the required signal-processing operations, such as filtration, are carried out if necessary. The method also comprises carrying out signal detection and decision-making concerning the acceptance as a heartbeat signal. According to the invention, the signal detection includes multichannel channel-specific detection for the purpose of identifying signal components of different channels, and the obtained channel-specific detected channel signals are used as input data during the decision-making stage.

Abstract: A multimode communications device includes an RF section and an analog-to-digital converter (ADC) located in a receive path between the RF section and a baseband section. The ADC includes a programmable signal converter core operable to perform ADC functions on a received RF signal in accordance with different types of mobile communication device operational modes, and further includes a multimode control function for programming the signal converter core as a function of a currently selected operational mode. The programmable signal converter core preferably includes a sigma-delta modulator, and a signal analysis function is provided for analyzing the received RF signal for dynamically programming the converter core to adapt to temporary signal and interference conditions by increasing or decreasing the performance of the signal converter.

Abstract: A multi-mode I/O circuit or cell (10) is provided for transmitting and receiving data between ICs, where each IC contains at least one of the I/O circuits. Each data link includes transmitter circuitry (12) and receiver circuitry (14). The transmitter circuitry sends data to a receiver circuitry in another IC, and the receiver circuitry receives data from a transmitter circuitry in another IC. The II/O circuit is constructed with CMOS-based transistors (e.g., CMOS or BiCMOS) that are selectively interconnected together by a plurality of switches to operate as two single-ended, current or voltage mode links, or as a single differential current or voltage mode link. In the preferred embodiment the transmitter circuitry sends data to the receiver circuitry in another IC over a first pair of adjacently disposed conductors, and the receiver circuitry receives data from the transmitter circuitry in another IC over a second pair of adjacently disposed conductors.

Abstract: A method and arrangement for blood pressure measurement are disclosed. In the method, a variable, compressive, acting pressure is applied to a compression, such as a person's extremity, by a pressure generator, and simultaneously, the effect of the variable acting pressure on the extremity is measured at a second point, the second point being farther from the heart than the compression point. The method determines diastolic and systolic pressure. The measured value of the variable acting pressure acting on the compression point is transferred to an interpreting unit, which also receives a pressure pulse generated by the heart. The pressure pulse is measured by a sensor at the second point for determining the effect of the variable acting pressure on the extremity. Further, diastolic pressure is determined int he interpreting unit based on the variable acting pressure, as the pressure when the interpreting unit detects a change in a trend of a characteristic of the pressure pulse indicative of magnitude.

Abstract: A multimode communications device includes an RF section and an analog-to-digital converter (ADC) located in a receive path between the RF section and a baseband section. The ADC includes a programmable signal converter core operable to perform ADC functions on a received RF signal in accordance with different types of mobile communication device operational modes, and further includes a multimode control function for programming the signal converter core as a function of a currently selected operational mode. The programmable signal converter core preferably includes a sigma-delta modulator, and a signal analysis function is provided for analyzing the received RF signal for dynamically programming the converter core to adapt to temporary signal and interference conditions by increasing or decreasing the performance of the signal converter.

Abstract: Disclosed is a method and apparatus for performing Dynamic Element Matching (DEM). The method operates to input a plurality of digital values and, for each value, to generate a plurality of N signals individual ones of which are intended to drive one of a plurality of N elements. The plurality of signals are generated so as to average the usage of individual ones of the N elements over time. The method further periodically rearranges the plurality of N signals so as to suppress the generation of undesired periodicities or tones in the usage of the N elements, and without affecting the averaging of the usage of the N elements. Preferably the periodic rearrangement occurs only at a time when the usage of the N elements is indicated as being averaged using, for example, an enable signal that is input to a secondary DEM block from a primary DEM block.

Abstract: Disclosed is a method for charging a battery and circuitry for performing the method. The method includes steps of: (A) generating at a first node a battery charge current (Icharge) for charging the battery; (B) generating at a second node a replica current (Irep) from Icharge, where Irep<Icharge; and (C) operating a closed loop current sink for sinking Irep, where a digital output of said closed loop current sink is a measure of the magnitude of Icharge. In the preferred embodiment the digital output is input to a control circuit for controlling the generation of Icharge. Also in the preferred embodiment the closed loop current sink is constructed from a multi-stage DAC that is driven by an output of an n-level digital filter that is incremented or decremented as a function of a voltage difference between the first node and the second node. Preferably the multi-stage DAC is a multi-stage current steering DAC, and the n-level digital filter is constructed using an up/down counter.

Abstract: Disclosed is a method and apparatus for performing Dynamic Element Matching (DEM). The method operates to input a plurality of digital values and, for each value, to generate a plurality of N signals individual ones of which are intended to drive one of a plurality of N elements. The plurality of signals are generated so as to average the usage of individual ones of the N elements over time. The method further periodically rearranges the plurality of N signals so as to suppress the generation of undesired periodicities or tones in the usage of the N elements, and without affecting the averaging of the usage of the N elements. Preferably the periodic rearrangement occurs only at a time when the usage of the N elements is indicated as being averaged using, for example, an enable signal that is input to a secondary DEM block from a primary DEM block.

Abstract: An N-level quantizer circuit has an analog input terminal and N−1 digital output terminals, and includes a sampling circuit coupled to the input terminal for providing a sampled input voltage signal; at least one preamplifier stage for converting the sampled input voltage signal to a current signal and providing an amplified sampled input signal; and N−1 comparator stages each having an input coupled to an output of the at least one preamplifier stage and sharing the input current equally. Individual ones of the N−1 comparator stages operate to compare the amplified sampled signal to an associated one of N−1 reference signals. The quantizer further includes N−1 latches, individual ones of which latch an output state of one of the N−1 comparators and have an output coupled to one of the N−1 digital output terminals of the quantizer circuit.

Abstract: Disclosed is a method and class D amplifier circuitry for compensating a pulse width modulated (PWM) signal. The method includes steps of generating a PWM signal for application to a driver stage; obtaining a filtered difference between the PWM signal and a version of the same PWM signal after the driver stage; generating a correction signal that is indicative of a sign of the filtered difference; and using the correction signal for adjusting at least one of the leading edge or the trailing edge of the PWM signal so as to compensate the version of the same PWM signal after the driver stage. The steps of obtaining and generating include steps of RC filtering, digital comparison and digital filtering. In the preferred embodiment the step of generating generates a one-bit correction signal. The correction signal is used to compensate the version of the same PWM signal after the driver stage for driver stage non-linearities and for power supply noise and variations.

Abstract: A method is disclosed for operating a sigma-delta modulator of a type that includes a loop filter followed by a quantizer, as is a sigma-delta modulator that operates in accordance with the method. The method includes steps of (a) sampling an amplitude of an input signal to the loop filter; and (b) generating a dither current signal for summation with a quantizer current signal, where the dither current signal is generated to have a pseudorandom amplitude that is modulated so as to be inversely proportional to the sampled amplitude of the input signal. The step of generating operates at least one linear feedback shift register to control the on and off states of a plurality of current sources forming a DAC and, hence, the amplitude of the dither current signal, and may further select the polarity of the dither current signal.

Abstract: The invention relates to a method and an apparatus for identifying a heartbeat. In the method, an arterial pressure signal is measured in the form of multichannel measurement, and the required signal-processing operations, such as filtration, are carried out if necessary. The method also comprises carrying out signal detection and decision-making concerning the acceptance as a heartbeat signal. According to the invention, the signal detection includes multichannel channel-specific detection for the purpose of identifying signal components of different channels, and the obtained channel-specific detected channel signals are used as input data during the decision-making stage.

Abstract: A multilevel quantizer is provided in combination with dynamic element matching (DEM) circuitry in a multibit sigma-delta modulator. The DEM circuitry is implemented in a divided manner as two major component parts: at least one current mode DEM switch matrix (SM), and an associated DEM decision logic block that implements the DEM control algorithm and that controls the SM. The DEM decision logic block is removed from the delay sensitive sigma-delta feedback loop, while the DEM SM remains within the feedback loop. Also described is a convenient and efficient technique to implement the DEM SM, using current steering logic within the multibit quantizer. In this case one or more DEM switching matrices may be provided within the quantizer for reordering the N−1 digital output bits of the N-level quantizer.

Abstract: Disclosed is a method for charging a battery and circuitry for performing the method. The method includes steps of: (A) generating at a first node a battery charge current (Icharge) for charging the battery; (B) generating at a second node a replica current (Irep) from Icharge, where Irep<Icharge; and (C) operating a closed loop current sink for sinking Irep, where a digital output of said closed loop current sink is a measure of the magnitude of Icharge. In the preferred embodiment the digital output is input to a control circuit for controlling the generation of Icharge. Also in the preferred embodiment the closed loop current sink is constructed from a multi-stage DAC that is driven by an output of an n-level digital filter that is incremented or decremented as a function of a voltage difference between the first node and the second node. Preferably the multi-stage DAC is a multi-stage current steering DAC, and the n-level digital filter is constructed using an up/down counter.

Abstract: Disclosed is a method and class D amplifier circuitry for compensating a pulse width modulated (PWM) signal. The method includes steps of generating a PWM signal for application to a driver stage; obtaining a filtered difference between the PWM signal and a version of the same PWM signal after the driver stage; generating a correction signal that is indicative of a sign of the filtered difference; and using the correction signal for adjusting at least one of the leading edge or the trailing edge of the PWM signal so as to compensate the version of the same PWM signal after the driver stage. The steps of obtaining and generating include steps of RC filtering, digital comparison and digital filtering. In the preferred embodiment the step of generating generates a one-bit correction signal. The correction signal is used to compensate the version of the same PWM signal after the driver stage for driver stage non-linearities and for power supply noise and variations.

Abstract: Disclosed is a method for charging a battery and circuitry for performing the method. The method includes steps of: (a) generating a charging current (Ich) for a battery; (b) generating a replica current (Irep) of Ich, where Irep=Ich/N, where N>1; (c) measuring a voltage drop induced by Irep across a measurement resistance; and (d) using the measured voltage drop for controlling a magnitude of Ich. Preferably N is greater than about 10, more preferably N is greater than about 100, and in the most preferred embodiment N is in a range of about 100 to about 1000. The step of generating the charging current (Ich) includes a step of operating a first device having an input node coupled to a source of charging current, the step of generating the replica current (Irep) includes a step of operating a second device having an input node coupled to the source of charging current; wherein the first device and the second device are both driven with the same control signal.

Abstract: The invention relates to a method and an apparatus for identifying a heartbeat. In the method, an arterial pressure signal is measured in the form of multichannel measurement, and the required signal-processing operations, such as filtration, are carried out if necessary. The method also comprises carrying out signal detection and decision-making concerning the acceptance as a heartbeat signal. According to the invention, the signal detection includes multichannel channel-specific detection for the purpose of identifying signal components of different channels, and the obtained channel-specific detected channel signals are used as input data during the decision-making stage.