Abstract: For speeding up the short-circuit and component test phase when testing electrical modules on a flying probe tester that includes contacting elements movable in all directions over a respective line networks of the electrical module, it is proposed that, at the beginning of the testing phase, such groups of contact points be contacted. Further, a respective line network-to-ground/potential connection for respective measurement threat is produced with respect to all line networks occurring on the electrical module under test.

Abstract: In particular in automatic testing equipment for integrated circuits, all signal sections at the test piece joint should ideally be of the same electrical length. The signal sections used in the test consist, in the case of reception, of cable, comparator, error logic, etc. If the signal sections are of different electrical durations, then in the case of reception, the transmitted signal must be connected. In a process for determining the electrical duration of signal sections, each of which has a transmitter and a receiver and at the end connecting points for example for an integrated circuit, the connecting points (AS) of all signal sections (SS) are short-circuited, all receivers up to the receiver of the signal section to be measured are then switched off, all transmitters up to the transmitter of the signal section to be measured are switched on and simultaneously emit a pulse which is transmitted to the connecting point.

Abstract: A test data generator and a test data converter are provided for generating test data words which are allocated to the terminal elements of a card module having electronic components. Dependent on a test program, the test data generator generates one or more test data vectors per test step to be executed. The test data converter generates the test data words from a test data vector or from further test information, and allocates individual bits of a test vector or of the test information to individual terminal elements of the unit under test. The allocation of the individual bits of the test vector or of the test information to the individual terminal elements of the unit under test can be freely set.