Patents by Inventor Anuj Grover
Anuj Grover has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240045589Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.Type: ApplicationFiled: October 17, 2023Publication date: February 8, 2024Applicants: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.Inventors: Nitin CHAWLA, Giuseppe DESOLI, Anuj GROVER, Thomas BOESCH, Surinder Pal SINGH, Manuj AYODHYAWASI
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Patent number: 11836346Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.Type: GrantFiled: May 12, 2022Date of Patent: December 5, 2023Assignees: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.Inventors: Nitin Chawla, Giuseppe Desoli, Anuj Grover, Thomas Boesch, Surinder Pal Singh, Manuj Ayodhyawasi
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Patent number: 11829730Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.Type: GrantFiled: September 8, 2022Date of Patent: November 28, 2023Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Nitin Chawla, Tanmoy Roy, Anuj Grover, Giuseppe Desoli
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Patent number: 11823771Abstract: A system includes a random access memory organized into individually addressable words. Streaming access control circuitry is coupled to word lines of the random access memory. The streaming access control circuitry responds to a request to access a plurality of individually addressable words of a determined region of the random access memory by generating control signals to drive the word lines to streamingly access the plurality of individually addressable words of the determined region. The request indicates an offset associated with the determined region and a pattern associated with the streaming access.Type: GrantFiled: January 26, 2021Date of Patent: November 21, 2023Assignees: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.Inventors: Nitin Chawla, Thomas Boesch, Anuj Grover, Surinder Pal Singh, Giuseppe Desoli
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Publication number: 20230350483Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.Type: ApplicationFiled: June 21, 2023Publication date: November 2, 2023Applicants: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.Inventors: Nitin CHAWLA, Anuj GROVER, Giuseppe DESOLI, Kedar Janardan DHORI, Thomas BOESCH, Promod KUMAR
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Patent number: 11798615Abstract: A memory cell that performs in-memory compute operations, includes a pair of cross-coupled inverters and a pair of transistors for selective performance of read/write/hold operations associated with logic states of the pair of cross-coupled inverters. The memory cell further includes a set of transistors that are gate coupled to and symmetrically arranged about the pair of cross coupled inverters. Output nodes of the memory cell are located at terminals of the set of transistors and provide output based on logic states of the pair of cross coupled inverters and input nodes provided between pairs of the set of transistors. A memory cell array may be generated having a high density arrangement memory cells that can perform in-memory compute operations. The memory cells can be arranged as a neural network including a set of memory cell networks that provide logic output operations based on logic states of the respective memory cells.Type: GrantFiled: April 15, 2022Date of Patent: October 24, 2023Assignee: STMicroelectronics International N.V.Inventors: Anuj Grover, Tanmoy Roy
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Patent number: 11776650Abstract: A memory calibration system includes a memory array having a plurality of memory cells, a sensing circuit coupled to the memory array, and calibration circuitry. A pattern of test data is applied to the memory array in order to generate calibration information based on output provided by the first sensing circuit in response to the application of the pattern of test data to the memory array. The generated calibration information is stored in a distributed manner within memory cells of the memory array. Some of the generated calibration information may be combined with data values stored in the plurality of memory cells as part of one or more operations on the stored data values.Type: GrantFiled: June 22, 2022Date of Patent: October 3, 2023Assignee: STMicroelectronics International N.V.Inventors: Tanmoy Roy, Anuj Grover
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Patent number: 11749343Abstract: A memory management circuit stores information indicative of reliability-types of regions of a memory array. The memory management circuitry responds to a request to allocate memory in the memory array to a process by determining a request type associated with the request to allocate memory. Memory of the memory array is allocated to the process based on the request type associated with the request to allocate memory and the stored information indicative of reliability-types of regions of the memory array. The memory array may be a shared memory array. The memory array may be organized into rows and columns, and the regions of the memory array may be the rows of the memory array.Type: GrantFiled: January 18, 2022Date of Patent: September 5, 2023Assignee: STMicroelectronics International N.V.Inventors: Nitin Chawla, Tanmoy Roy, Anuj Grover
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Patent number: 11726543Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.Type: GrantFiled: December 3, 2020Date of Patent: August 15, 2023Assignees: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.Inventors: Nitin Chawla, Anuj Grover, Giuseppe Desoli, Kedar Janardan Dhori, Thomas Boesch, Promod Kumar
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Publication number: 20230186983Abstract: An in-memory compute (IMC) device includes an array of memory cells and control logic coupled to the array of memory cells. The array of memory cells is arranged as a plurality of rows of cells intersecting a plurality of columns of cells. The array of memory cells includes a first subset of memory cells forming a plurality of computational engines at intersections of rows and columns of the first subset of the array of memory cells. The array also includes a second subset of memory cells forming a plurality of bias engines. The control logic, in operation, generates control signals to control the array of memory cells to perform a plurality of IMC operations using the computational engines, store results of the plurality of IMC operations in memory cells of the array, and computationally combine results of the plurality of IMC operations with respective bias values using the bias engines.Type: ApplicationFiled: February 10, 2023Publication date: June 15, 2023Applicant: STMicroelectronics International N.V.Inventors: Anuj GROVER, Tanmoy ROY, Nitin CHAWLA
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Patent number: 11605424Abstract: An in-memory compute (IMC) device includes a compute array having a first plurality of cells. The compute array is arranged as a plurality of rows of cells intersecting a plurality of columns of cells. Each cell of the first plurality of cells is identifiable by its corresponding row and column. The IMC device also includes a plurality of computation engines and a plurality of bias engines. Each computation engine is respectively formed in a different one of a second plurality of cells, wherein the second plurality of cells is formed from cells of the first plurality. Each computation engine is formed at a respective row and column intersection. Each bias engine of the plurality of bias engines is arranged to computationally combine an output from at least one of the plurality of computation engines with a respective bias value.Type: GrantFiled: July 14, 2021Date of Patent: March 14, 2023Assignee: STMicroelectronics International N.V.Inventors: Anuj Grover, Tanmoy Roy, Nitin Chawla
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Publication number: 20230004354Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.Type: ApplicationFiled: September 8, 2022Publication date: January 5, 2023Applicants: STMICROELECTRONICS S.R.L., STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Nitin CHAWLA, Tanmoy ROY, Anuj GROVER, Giuseppe DESOLI
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Patent number: 11474788Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.Type: GrantFiled: June 2, 2020Date of Patent: October 18, 2022Assignees: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.Inventors: Nitin Chawla, Tanmoy Roy, Anuj Grover, Giuseppe Desoli
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Publication number: 20220328118Abstract: A memory calibration system includes a memory array having a plurality of memory cells, a sensing circuit coupled to the memory array, and calibration circuitry. A pattern of test data is applied to the memory array in order to generate calibration information based on output provided by the first sensing circuit in response to the application of the pattern of test data to the memory array. The generated calibration information is stored in a distributed manner within memory cells of the memory array. Some of the generated calibration information may be combined with data values stored in the plurality of memory cells as part of one or more operations on the stored data values.Type: ApplicationFiled: June 22, 2022Publication date: October 13, 2022Applicant: STMicroelectronics International N.V.Inventors: Tanmoy ROY, Anuj GROVER
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Publication number: 20220269410Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.Type: ApplicationFiled: May 12, 2022Publication date: August 25, 2022Applicants: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.Inventors: Nitin CHAWLA, Giuseppe DESOLI, Anuj GROVER, Thomas BOESCH, Surinder Pal SINGH, Manuj AYODHYAWASI
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Publication number: 20220238150Abstract: A memory cell that performs in-memory compute operations, includes a pair of cross-coupled inverters and a pair of transistors for selective performance of read/write/hold operations associated with logic states of the pair of cross-coupled inverters. The memory cell further includes a set of transistors that are gate coupled to and symmetrically arranged about the pair of cross coupled inverters. Output nodes of the memory cell are located at terminals of the set of transistors and provide output based on logic states of the pair of cross coupled inverters and input nodes provided between pairs of the set of transistors. A memory cell array may be generated having a high density arrangement memory cells that can perform in-memory compute operations. The memory cells can be arranged as a neural network including a set of memory cell networks that provide logic output operations based on logic states of the respective memory cells.Type: ApplicationFiled: April 15, 2022Publication date: July 28, 2022Applicant: STMicroelectronics International N.V.Inventors: Anuj GROVER, Tanmoy ROY
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Patent number: 11398289Abstract: A memory calibration system includes a memory array having a plurality of memory cells, a sensing circuit coupled to the memory array, and calibration circuitry. A pattern of test data is applied to the memory array in order to generate calibration information based on output provided by the first sensing circuit in response to the application of the pattern of test data to the memory array. The generated calibration information is stored in a distributed manner within memory cells of the memory array. Some of the generated calibration information may be combined with data values stored in the plurality of memory cells as part of one or more operations on the stored data values.Type: GrantFiled: January 25, 2021Date of Patent: July 26, 2022Assignee: STMicroelectronics International N.V.Inventors: Tanmoy Roy, Anuj Grover
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Patent number: 11360667Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.Type: GrantFiled: September 4, 2020Date of Patent: June 14, 2022Assignees: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.Inventors: Nitin Chawla, Giuseppe Desoli, Anuj Grover, Thomas Boesch, Surinder Pal Singh, Manuj Ayodhyawasi
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Patent number: 11335397Abstract: A memory cell that performs in-memory compute operations, includes a pair of cross-coupled inverters and a pair of transistors for selective performance of read/write/hold operations associated with logic states of the pair of cross-coupled inverters. The memory cell further includes a set of transistors that are gate coupled to and symmetrically arranged about the pair of cross coupled inverters. Output nodes of the memory cell are located at terminals of the set of transistors and provide output based on logic states of the pair of cross coupled inverters and input nodes provided between pairs of the set of transistors. A memory cell array may be generated having a high density arrangement memory cells that can perform in-memory compute operations. The memory cells can be arranged as a neural network including a set of memory cell networks that provide logic output operations based on logic states of the respective memory cells.Type: GrantFiled: August 14, 2020Date of Patent: May 17, 2022Assignee: STMicroelectronics International N.V.Inventors: Anuj Grover, Tanmoy Roy
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Publication number: 20220139453Abstract: A memory management circuit stores information indicative of reliability-types of regions of a memory array. The memory management circuitry responds to a request to allocate memory in the memory array to a process by determining a request type associated with the request to allocate memory. Memory of the memory array is allocated to the process based on the request type associated with the request to allocate memory and the stored information indicative of reliability-types of regions of the memory array. The memory array may be a shared memory array. The memory array may be organized into rows and columns, and the regions of the memory array may be the rows of the memory array.Type: ApplicationFiled: January 18, 2022Publication date: May 5, 2022Applicant: STMicroelectronics International N.V.Inventors: Nitin CHAWLA, Tanmoy ROY, Anuj GROVER