Patents by Inventor Anuj Kohli
Anuj Kohli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11441804Abstract: A device for detecting a wire configuration connecting a thermostat and HVAC equipment includes fan controller circuitry, AC controller circuitry, switching circuitry, and processing circuitry. The fan controller circuitry is configured to operate a fan unit of the HVAC equipment using a G pin in a first wire configuration and using a K pin in a second wire configuration. The AC controller circuitry is configured to operate an AC unit of the HVAC equipment using a Y pin in the first wire configuration and the K pin in the second wire configuration. The switching circuitry is configured to refrain from electrically coupling the Y pin and the K pin in response to a deactivation signal. The processing circuitry is configured to determine the HVAC equipment is in the first wire configuration in response to determining the AC controller circuitry receives power while outputting the deactivation signal to the switching circuitry.Type: GrantFiled: December 18, 2019Date of Patent: September 13, 2022Assignee: Ademco Inc.Inventors: Hyunki Kim, Robert D. Juntunen, Jesus Omar Ponce, Liliana Reategui, Anuj Kohli, David Mulhouse
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Publication number: 20210190348Abstract: A system for detection of equipment connections to a thermostat. The thermostat may have one or more terminals with a one-to-one connection to one or more loads respectively of heating, ventilation and/or air conditioning equipment, and one or more terminals with a one-to-one connection to electrical power. One or more detectors may be connected one-to-one to each of the one or more terminals, respectively, for connection to the one or more loads, and the one or more connections to the electrical power. Each detector may be connected to a processor. Each detector may be configured to provide a signal to the processor relative to a corresponding terminal indicating a status of a connection of the terminal to a load or to the electrical power.Type: ApplicationFiled: December 18, 2019Publication date: June 24, 2021Inventors: Jiri Sapak, Mohammad A. Aljabari, David Mulhouse, Daniel Becvar, Tracy Lentz, Liliana Reategui, Anuj Kohli
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Publication number: 20210190356Abstract: A device for detecting a wire configuration connecting a thermostat and HVAC equipment includes fan controller circuitry, AC controller circuitry, switching circuitry, and processing circuitry. The fan controller circuitry is configured to operate a fan unit of the HVAC equipment using a G pin in a first wire configuration and using a K pin in a second wire configuration. The AC controller circuitry is configured to operate an AC unit of the HVAC equipment using a Y pin in the first wire configuration and the K pin in the second wire configuration. The switching circuitry is configured to refrain from electrically coupling the Y pin and the K pin in response to a deactivation signal. The processing circuitry is configured to determine the HVAC equipment is in the first wire configuration in response to determining the AC controller circuitry receives power while outputting the deactivation signal to the switching circuitry.Type: ApplicationFiled: December 18, 2019Publication date: June 24, 2021Inventors: Hyunki Kim, Robert D. Juntunen, Jesus Omar Ponce, Liliana Reategui, Anuj Kohli, David Mulhouse
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Patent number: 9042164Abstract: A system may include circuitry and a magnetoresistive random access memory (MRAM) die including at least one MRAM cell. The circuitry may be configured to detect attempted tampering with the MRAM die and generate a signal based on the detected attempted tampering. The signal may be sufficient to damage or destroy at least one layer of the at least one MRAM cell or a fuse electrically connected to a read line of the at least one MRAM cell.Type: GrantFiled: March 26, 2012Date of Patent: May 26, 2015Assignee: Honeywell International Inc.Inventors: Romney R. Katti, James L. Tucker, Anuj Kohli
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Patent number: 8963590Abstract: A system for initializing circuitry is presented. The system employs a power-on reset circuit having a threshold voltage and a programmable switch circuit. The power-on reset circuit has a detector circuit for detecting a reference voltage, and a one-sided latch for generating an output voltage reflective of the reference voltage. The detector circuit has a threshold after which the one-sided latch is activated. The programmable switch circuit receives the output voltage of the power-on reset circuit and generates an enable signal and its complement based on the status of an internal fuse. The switch point of the power-on reset circuit provides for a rapid increase in output voltage that offsets parasitic leakage current in the programmable switch circuit that can result in improper enable signal output. A high resistance direct path to ground on an output node of the power-on reset circuit prevents residual charge from causing an undesired misfire.Type: GrantFiled: April 15, 2009Date of Patent: February 24, 2015Assignee: Honeywell International Inc.Inventors: Joe G. Guimont, David K. Nelson, Walter W. Heikkila, Anuj Kohli
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Magnetoresistive random access memory (MRAM) die including an integrated magnetic security structure
Patent number: 8854870Abstract: An MRAM die may include a first write line, a second write line, an MRAM cell disposed between the first write line and the second write line, and a magnetic security structure adjacent to the MRAM cell. The magnetic security structure may include a permanent magnetic layer and a soft magnetic layer.Type: GrantFiled: March 13, 2012Date of Patent: October 7, 2014Assignee: Honeywell International Inc.Inventors: Romney R. Katti, James L. Tucker, Anuj Kohli -
Patent number: 8811072Abstract: A magnetoresistive random access memory (MRAM) package may include an MRAM die, a package defining a cavity and an exterior surface, and a magnetic security structure disposed within the cavity or on the exterior surface of the package. The MRAM die may be disposed in the cavity of the package, and the magnetic security structure may include at least three layers including a permanent magnetic layer and a soft magnetic layer.Type: GrantFiled: March 13, 2012Date of Patent: August 19, 2014Assignee: Honeywell International Inc.Inventors: Romney R. Katti, James L. Tucker, Anuj Kohli
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Patent number: 8730715Abstract: A magnetoresistive random access memory (MRAM) die may include an MRAM cell, a reservoir defined by the MRAM die, and a chemical disposed in the reservoir. At least one boundary of the reservoir may be configured to be damaged in response to attempted tampering with the MRAM die, such that at least some of the chemical is released from the reservoir when the at least one boundary of the reservoir is damaged. In some examples, at least some of the chemical is configured to contact and alter or damage at least a portion of the MRAM cell when the chemical is released from the reservoir.Type: GrantFiled: March 26, 2012Date of Patent: May 20, 2014Assignee: Honeywell International Inc.Inventors: Romney R. Katti, James L. Tucker, Anuj Kohli
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Publication number: 20130250663Abstract: A system may include circuitry and a magnetoresistive random access memory (MRAM) die including at least one MRAM cell. The circuitry may be configured to detect attempted tampering with the MRAM die and generate a signal based on the detected attempted tampering. The signal may be sufficient to damage or destroy at least one layer of the at least one MRAM cell or a fuse electrically connected to a read line of the at least one MRAM cell.Type: ApplicationFiled: March 26, 2012Publication date: September 26, 2013Applicant: HONEYWELL INTERNATIONAL INC.Inventors: Romney R. Katti, James L. Tucker, Anuj Kohli
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Publication number: 20130250662Abstract: A magnetoresistive random access memory (MRAM) die may include an MRAM cell, a reservoir defined by the MRAM die, and a chemical disposed in the reservoir. At least one boundary of the reservoir may be configured to be damaged in response to attempted tampering with the MRAM die, such that at least some of the chemical is released from the reservoir when the at least one boundary of the reservoir is damaged. In some examples, at least some of the chemical is configured to contact and alter or damage at least a portion of the MRAM cell when the chemical is released from the reservoir.Type: ApplicationFiled: March 26, 2012Publication date: September 26, 2013Applicant: HONEYWELL INTERNATIONAL INC.Inventors: Romney R. Katti, James L. Tucker, Anuj Kohli
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MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) DIE INCLUDING AN INTEGRATED MAGNETIC SECURITY STRUCTURE
Publication number: 20130242646Abstract: An MRAM die may include a first write line, a second write line, an MRAM cell disposed between the first write line and the second write line, and a magnetic security structure adjacent to the MRAM cell. The magnetic security structure may include a permanent magnetic layer and a soft magnetic layer.Type: ApplicationFiled: March 13, 2012Publication date: September 19, 2013Applicant: HONEYWELL INTERNATIONAL INC.Inventors: Romney R. Katti, James L. Tucker, Anuj Kohli -
Publication number: 20130241014Abstract: A magnetoresistive random access memory (MRAM) package may include an MRAM die, a package defining a cavity and an exterior surface, and a magnetic security structure disposed within the cavity or on the exterior surface of the package. The MRAM die may be disposed in the cavity of the package, and the magnetic security structure may include at least three layers including a permanent magnetic layer and a soft magnetic layer.Type: ApplicationFiled: March 13, 2012Publication date: September 19, 2013Applicant: HONEYWELL INTERNATIONAL INC.Inventors: Romney R. Katti, James L. Tucker, Anuj Kohli
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Patent number: 7589308Abstract: A method and apparatus for regulating photocurrents is described. A photocurrent regulator may include a transistor having an associated cross-sectional area. The photocurrent regulator is coupled between an integrated circuit and a voltage source. When a dose rate event occurs within the integrated circuit, the photocurrent regulator, via the cross-sectional area, regulates a recombination path to the voltage source. Consequently, photocurrents within the integrated circuit are regulated, preventing permanent damage within the integrated circuit.Type: GrantFiled: September 1, 2006Date of Patent: September 15, 2009Assignee: Honeywell International Inc.Inventors: Harry H L Liu, Anuj Kohli, Michael S Liu
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Publication number: 20080309384Abstract: A system for initializing circuitry is presented. The system employs a power-on reset circuit having a threshold voltage and a programmable switch circuit. The power-on reset circuit has a detector circuit for detecting a reference voltage, and a one-sided latch for generating an output voltage reflective of the reference voltage. The detector circuit has a threshold after which the one-sided latch is activated. The programmable switch circuit receives the output voltage of the power-on reset circuit and generates an enable signal arid its complement based on the status of an internal fuse. The switch point of the power-on reset circuit provides for a rapid increase in output voltage, offsetting parasitic leakage current in the programmable switch circuit that can result in improper enable signal output.Type: ApplicationFiled: June 13, 2007Publication date: December 18, 2008Applicant: Honeywell International Inc.Inventors: Joe G. Guimont, David K. Nelson, Walter W. Heikkila, Anuj Kohli
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Publication number: 20080054360Abstract: A method and apparatus for regulating photocurrents is described. A photocurrent regulator may include a transistor having an associated cross-sectional area. The photocurrent regulator is coupled between an integrated circuit and a voltage source. When a dose rate event occurs within the integrated circuit, the photocurrent regulator, via the cross-sectional area, regulates a recombination path to the voltage source. Consequently, photocurrents within the integrated circuit are regulated, preventing permanent damage within the integrated circuit.Type: ApplicationFiled: September 1, 2006Publication date: March 6, 2008Applicant: HONEYWELL INTERNATIONAL INC.Inventors: Harry HL Liu, Anuj Kohli, Michael S. Liu
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Patent number: 6400257Abstract: A high performance CMOS comparator circuit is integrated with a bypass function allowing comparing first and second data sets (A & B) with a high data width (more than 30 and illustrated as 48 bits). In many cases, it is often required to compare not only sets A&B but also set A with an additional bypass set, and the preferred circuit embodiment permits this to be achieved.Type: GrantFiled: July 26, 2000Date of Patent: June 4, 2002Assignee: International Business Machines CorporationInventors: Yuen H. Chan, Anuj Kohli, John R. Rawlins