Patents by Inventor Anuj Soni
Anuj Soni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9523033Abstract: A method for the synthesis of OSL grade polycrystalline mass of ceramic materials with dopant C involving source ceramic material preferably in its readily available powder form comprising the steps of melting of the said ceramic material in graphite environment including a graphite crucible/container in vacuum; and obtaining there from polycrystalline aggregate by rapid solidification of said melt to thereby provide said polycrystalline mass of ceramic materials with dopant C of optically stimulated luminescence grade. The said powder form of the ceramic material is compacted and formed into pellets before subjecting to melting.Type: GrantFiled: June 24, 2013Date of Patent: December 20, 2016Assignee: THE SECRETARY, DEPARTMENT OF ATOMIC ENERGYInventors: Kunal Purnachandra Muthe, Mukund Shrinivas Kulkarni, Anuj Soni, Ajay Singh, Narender Singh Rawat, Devesh Ramdhar Mishra, Ratna Pradeep, Shovit Bhattacharya, Deva Nand Sharma, Shiv Kumar Gupta
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Patent number: 8959290Abstract: Methods and apparatus are provided for reusing snoop responses and data phase results in a cache controller. A cache controller receives a broadcast combined snoop response from a bus controller, wherein the broadcast combined snoop response corresponds to an incoming bus transaction BTR1 corresponding to a cache transaction CTR1 for an entry in at least one cache and wherein the combined snoop response is a combination of at least one snoop response from a plurality of cache controllers; receives broadcast cache line data from a source cache as instructed by the bus controller for the entry during a data phase; and processes a subsequent cache transaction CTR2 for the entry based on one or more of the broadcast combined snoop response and the broadcast cache line data.Type: GrantFiled: February 21, 2012Date of Patent: February 17, 2015Assignee: LSI CorporationInventors: Vidyalakshmi Rajagopalan, Archna Rai, Sharath Kashyap, Anuj Soni
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Patent number: 8886889Abstract: Methods and apparatus are provided for reusing snoop responses and data phase results in a bus controller. A bus controller receives an incoming bus transaction BTR1 corresponding to an incoming cache transaction CTR1 for an entry in at least one cache; issues a snoop request with a cache line address of the incoming bus transaction BTR1 for the entry to a plurality of cache controllers; collects at least one snoop response from the plurality of cache controllers; broadcasts a combined snoop response to the plurality of cache controllers, wherein the combined snoop response is a combination of the snoop responses from the plurality of cache controllers; and broadcasts cache line data from a source cache for the entry during a data phase to the plurality of cache controllers, wherein a subsequent cache transaction CTR2 for the entry is processed based on the broadcast combined snoop response and the broadcast cache line data.Type: GrantFiled: February 21, 2012Date of Patent: November 11, 2014Assignee: LSI CorporationInventors: Vidyalakshmi Rajagopalan, Archna Rai, Sharath Kashyap, Anuj Soni
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Publication number: 20140209712Abstract: A method for the synthesis of OSL grade polycrystalline mass of ceramic materials with dopant C involving source ceramic material preferably in its readily available powder form comprising the steps of melting of the said ceramic material in graphite environment including a graphite crucible/container in vacuum; and obtaining there from polycrystalline aggregate by rapid solidification of said melt to thereby provide said polycrystalline mass of ceramic materials with dopant C of optically stimulated luminescence grade. The said powder form of the ceramic material is compacted and formed into pellets before subjecting to melting.Type: ApplicationFiled: June 24, 2013Publication date: July 31, 2014Inventors: Kunal Purnachandra MUTHE, Mukund Shrinivas KULKARNI, Anuj SONI, Ajay SINGH, Narender Singh RAWAT, Devesh Ramdhar MISHRA, Ratna PRADEEP, Shovit BHATTACHARYA, Deva Nand SHARMA, Shiv Kumar GUPTA
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Publication number: 20140084981Abstract: Systems and methods are provided for designing integrated circuits using configurable delay cell (CDC) circuits that serve to expedite timing closure for an integrated circuit (IC) design by eliminating the need to iteratively repeat various design steps such as placement, signal distribution network synthesis, and routing. CDC circuits include footprint compatible circuits having different delay characteristics, which may be included as part of a standard cell library for designing integrated circuits. A CDC circuit can be used in an IC design to add a desired delay to a given clock path or data path, and then replaced with another footprint compatible CDC circuit to increase or decrease the delay in the given clock or data path to meet one or more timing requirements and achieve timing closure without having to repeat placement, signal distribution network synthesis or routing steps.Type: ApplicationFiled: October 18, 2013Publication date: March 27, 2014Applicant: LSI CorporationInventors: Anuj Soni, Vinaya Gudeangadi
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Publication number: 20140032858Abstract: Methods and apparatus are provided for cache line sharing among cache controllers. A cache comprises a plurality of cache lines; and a cache controller for sharing at least one of the cache lines with one or more additional caches, wherein a given cache line shared by a plurality of caches corresponds to a given set of physical addresses in a main memory. The cache controller optionally maintains an ownership control signal indicating which portions of the at least one cache line are controlled by the cache and a validity control signal indicating whether each portion of the at least one cache line is valid. Each cache line can be in one of a plurality of cache coherence states, including a modified partial state and a shared partial state.Type: ApplicationFiled: July 25, 2012Publication date: January 30, 2014Inventors: Vidyalakshmi Rajagopalan, Archna Rai, Anuj Soni, Sharath Kashyap
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Publication number: 20140032857Abstract: Shared cache line data is merged in a bus controller by issuing a snoop request to a plurality of cache controllers with a cache line address for which a bus transaction is performed; collecting snoop responses from the plurality of cache controllers, wherein a snoop response from a given cache controller comprises a cache state of the cache line address in a given cache associated with the given cache controller, and an ownership control signal identifying which portions of the cache line are controlled by the given cache; collecting data responses from the cache controllers, wherein the data response from a given cache controller comprises a data value from the cache line address; merging the data values from the cache controllers based on the ownership control signals to obtain a merged data value; and broadcasting the merged data value to the cache controllers.Type: ApplicationFiled: July 25, 2012Publication date: January 30, 2014Inventors: Vidyalakshmi Rajagopalan, Archna Rai, Anuj Soni, Sharath Kashyap
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Patent number: 8607180Abstract: An integrated circuit (IC) or a block of an IC is routed. The signals of the netlist to be routed are grouped according the signal properties. A signal property may be the time or clock used to initiate the switching of the signal. The signals of each group are routed successively. This causes the signals of later groups to be routed between the signals of previous groups thereby providing shielding between signals lines of the same group.Type: GrantFiled: May 9, 2012Date of Patent: December 10, 2013Assignee: LSI CorporationInventor: Anuj Soni
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Patent number: 8595668Abstract: Systems and methods are provided for designing integrated circuits using configurable delay cell (CDC) circuits that serve to expedite timing closure for an integrated circuit (IC) design by eliminating the need to iteratively repeat various design steps such as placement, signal distribution network synthesis, and routing. CDC circuits include footprint compatible circuits having different delay characteristics, which may be included as part of a standard cell library for designing integrated circuits. A CDC circuit can be used in an IC design to add a desired delay to a given clock path or data path, and then replaced with another footprint compatible CDC circuit to increase or decrease the delay in the given clock or data path to meet one or more timing requirements and achieve timing closure without having to repeat placement, signal distribution network synthesis or routing steps.Type: GrantFiled: September 26, 2012Date of Patent: November 26, 2013Assignee: LSI CorporationInventors: Anuj Soni, Vinaya Gudeangadi
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Publication number: 20130305203Abstract: An integrated circuit (IC) or a block of an IC is routed. The signals of the netlist to be routed are grouped according the signal properties. A signal property may be the time or clock used to initiate the switching of the signal. The signals of each group are routed successively. This causes the signals of later groups to be routed between the signals of previous groups thereby providing shielding between signals lines of the same group.Type: ApplicationFiled: May 9, 2012Publication date: November 14, 2013Applicant: LSI CORPORATIONInventor: Anuj Soni
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Publication number: 20130219128Abstract: Methods and apparatus are provided for reusing snoop responses and data phase results in a bus controller. A bus controller receives an incoming bus transaction BTR1 corresponding to an incoming cache transaction CTR1 for an entry in at least one cache; issues a snoop request with a cache line address of the incoming bus transaction BTR1 for the entry to a plurality of cache controllers; collects at least one snoop response from the plurality of cache controllers; broadcasts a combined snoop response to the plurality of cache controllers, wherein the combined snoop response is a combination of the snoop responses from the plurality of cache controllers; and broadcasts cache line data from a source cache for the entry during a data phase to the plurality of cache controllers, wherein a subsequent cache transaction CTR2 for the entry is processed based on the broadcast combined snoop response and the broadcast cache line data.Type: ApplicationFiled: February 21, 2012Publication date: August 22, 2013Inventors: Vidyalakshmi Rajagopalan, Archna Rai, Sharath Kashyap, Anuj Soni
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Publication number: 20130219129Abstract: Methods and apparatus are provided for reusing snoop responses and data phase results in a cache controller. A cache controller receives a broadcast combined snoop response from a bus controller, wherein the broadcast combined snoop response corresponds to an incoming bus transaction BTR1 corresponding to a cache transaction CTR1 for an entry in at least one cache and wherein the combined snoop response is a combination of at least one snoop response from a plurality of cache controllers; receives broadcast cache line data from a source cache as instructed by the bus controller for the entry during a data phase; and processes a subsequent cache transaction CTR2 for the entry based on one or more of the broadcast combined snoop response and the broadcast cache line data.Type: ApplicationFiled: February 21, 2012Publication date: August 22, 2013Inventors: Vidyalakshmi Rajagopalan, Archna Rai, Sharath Kashyap, Anuj Soni
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Publication number: 20130103903Abstract: Methods and apparatus are provided for reusing prior tag search results in a cache controller. A cache controller is disclosed that receives an incoming request for an entry in the cache having a first tag; determines if there is an existing entry in a buffer associated with the cache having the first tag; and reuses a tag access result from the existing entry in the buffer having the first tag for the incoming request. An indicator can be maintained in the existing entry to indicate whether the tag access result should be retained. Tag access results can optionally be retained in the buffer after completion of a corresponding request. The tag access result can be reused by (i) reallocating the existing entry to the incoming request if the indicator in the existing entry indicates that the tag access result should be retained; and/or (ii) copying the tag access result from the existing entry to a buffer entry allocated to the incoming request if a hazard is detected.Type: ApplicationFiled: October 20, 2011Publication date: April 25, 2013Inventors: Vidyalakshmi Rajagopalan, Archna Raj, Sharath Kashyap, Anuj Soni