Patents by Inventor Anuj Soni

Anuj Soni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9523033
    Abstract: A method for the synthesis of OSL grade polycrystalline mass of ceramic materials with dopant C involving source ceramic material preferably in its readily available powder form comprising the steps of melting of the said ceramic material in graphite environment including a graphite crucible/container in vacuum; and obtaining there from polycrystalline aggregate by rapid solidification of said melt to thereby provide said polycrystalline mass of ceramic materials with dopant C of optically stimulated luminescence grade. The said powder form of the ceramic material is compacted and formed into pellets before subjecting to melting.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: December 20, 2016
    Assignee: THE SECRETARY, DEPARTMENT OF ATOMIC ENERGY
    Inventors: Kunal Purnachandra Muthe, Mukund Shrinivas Kulkarni, Anuj Soni, Ajay Singh, Narender Singh Rawat, Devesh Ramdhar Mishra, Ratna Pradeep, Shovit Bhattacharya, Deva Nand Sharma, Shiv Kumar Gupta
  • Patent number: 8959290
    Abstract: Methods and apparatus are provided for reusing snoop responses and data phase results in a cache controller. A cache controller receives a broadcast combined snoop response from a bus controller, wherein the broadcast combined snoop response corresponds to an incoming bus transaction BTR1 corresponding to a cache transaction CTR1 for an entry in at least one cache and wherein the combined snoop response is a combination of at least one snoop response from a plurality of cache controllers; receives broadcast cache line data from a source cache as instructed by the bus controller for the entry during a data phase; and processes a subsequent cache transaction CTR2 for the entry based on one or more of the broadcast combined snoop response and the broadcast cache line data.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: February 17, 2015
    Assignee: LSI Corporation
    Inventors: Vidyalakshmi Rajagopalan, Archna Rai, Sharath Kashyap, Anuj Soni
  • Patent number: 8886889
    Abstract: Methods and apparatus are provided for reusing snoop responses and data phase results in a bus controller. A bus controller receives an incoming bus transaction BTR1 corresponding to an incoming cache transaction CTR1 for an entry in at least one cache; issues a snoop request with a cache line address of the incoming bus transaction BTR1 for the entry to a plurality of cache controllers; collects at least one snoop response from the plurality of cache controllers; broadcasts a combined snoop response to the plurality of cache controllers, wherein the combined snoop response is a combination of the snoop responses from the plurality of cache controllers; and broadcasts cache line data from a source cache for the entry during a data phase to the plurality of cache controllers, wherein a subsequent cache transaction CTR2 for the entry is processed based on the broadcast combined snoop response and the broadcast cache line data.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: November 11, 2014
    Assignee: LSI Corporation
    Inventors: Vidyalakshmi Rajagopalan, Archna Rai, Sharath Kashyap, Anuj Soni
  • Publication number: 20140209712
    Abstract: A method for the synthesis of OSL grade polycrystalline mass of ceramic materials with dopant C involving source ceramic material preferably in its readily available powder form comprising the steps of melting of the said ceramic material in graphite environment including a graphite crucible/container in vacuum; and obtaining there from polycrystalline aggregate by rapid solidification of said melt to thereby provide said polycrystalline mass of ceramic materials with dopant C of optically stimulated luminescence grade. The said powder form of the ceramic material is compacted and formed into pellets before subjecting to melting.
    Type: Application
    Filed: June 24, 2013
    Publication date: July 31, 2014
    Inventors: Kunal Purnachandra MUTHE, Mukund Shrinivas KULKARNI, Anuj SONI, Ajay SINGH, Narender Singh RAWAT, Devesh Ramdhar MISHRA, Ratna PRADEEP, Shovit BHATTACHARYA, Deva Nand SHARMA, Shiv Kumar GUPTA
  • Publication number: 20140084981
    Abstract: Systems and methods are provided for designing integrated circuits using configurable delay cell (CDC) circuits that serve to expedite timing closure for an integrated circuit (IC) design by eliminating the need to iteratively repeat various design steps such as placement, signal distribution network synthesis, and routing. CDC circuits include footprint compatible circuits having different delay characteristics, which may be included as part of a standard cell library for designing integrated circuits. A CDC circuit can be used in an IC design to add a desired delay to a given clock path or data path, and then replaced with another footprint compatible CDC circuit to increase or decrease the delay in the given clock or data path to meet one or more timing requirements and achieve timing closure without having to repeat placement, signal distribution network synthesis or routing steps.
    Type: Application
    Filed: October 18, 2013
    Publication date: March 27, 2014
    Applicant: LSI Corporation
    Inventors: Anuj Soni, Vinaya Gudeangadi
  • Publication number: 20140032858
    Abstract: Methods and apparatus are provided for cache line sharing among cache controllers. A cache comprises a plurality of cache lines; and a cache controller for sharing at least one of the cache lines with one or more additional caches, wherein a given cache line shared by a plurality of caches corresponds to a given set of physical addresses in a main memory. The cache controller optionally maintains an ownership control signal indicating which portions of the at least one cache line are controlled by the cache and a validity control signal indicating whether each portion of the at least one cache line is valid. Each cache line can be in one of a plurality of cache coherence states, including a modified partial state and a shared partial state.
    Type: Application
    Filed: July 25, 2012
    Publication date: January 30, 2014
    Inventors: Vidyalakshmi Rajagopalan, Archna Rai, Anuj Soni, Sharath Kashyap
  • Publication number: 20140032857
    Abstract: Shared cache line data is merged in a bus controller by issuing a snoop request to a plurality of cache controllers with a cache line address for which a bus transaction is performed; collecting snoop responses from the plurality of cache controllers, wherein a snoop response from a given cache controller comprises a cache state of the cache line address in a given cache associated with the given cache controller, and an ownership control signal identifying which portions of the cache line are controlled by the given cache; collecting data responses from the cache controllers, wherein the data response from a given cache controller comprises a data value from the cache line address; merging the data values from the cache controllers based on the ownership control signals to obtain a merged data value; and broadcasting the merged data value to the cache controllers.
    Type: Application
    Filed: July 25, 2012
    Publication date: January 30, 2014
    Inventors: Vidyalakshmi Rajagopalan, Archna Rai, Anuj Soni, Sharath Kashyap
  • Patent number: 8607180
    Abstract: An integrated circuit (IC) or a block of an IC is routed. The signals of the netlist to be routed are grouped according the signal properties. A signal property may be the time or clock used to initiate the switching of the signal. The signals of each group are routed successively. This causes the signals of later groups to be routed between the signals of previous groups thereby providing shielding between signals lines of the same group.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: December 10, 2013
    Assignee: LSI Corporation
    Inventor: Anuj Soni
  • Patent number: 8595668
    Abstract: Systems and methods are provided for designing integrated circuits using configurable delay cell (CDC) circuits that serve to expedite timing closure for an integrated circuit (IC) design by eliminating the need to iteratively repeat various design steps such as placement, signal distribution network synthesis, and routing. CDC circuits include footprint compatible circuits having different delay characteristics, which may be included as part of a standard cell library for designing integrated circuits. A CDC circuit can be used in an IC design to add a desired delay to a given clock path or data path, and then replaced with another footprint compatible CDC circuit to increase or decrease the delay in the given clock or data path to meet one or more timing requirements and achieve timing closure without having to repeat placement, signal distribution network synthesis or routing steps.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: November 26, 2013
    Assignee: LSI Corporation
    Inventors: Anuj Soni, Vinaya Gudeangadi
  • Publication number: 20130305203
    Abstract: An integrated circuit (IC) or a block of an IC is routed. The signals of the netlist to be routed are grouped according the signal properties. A signal property may be the time or clock used to initiate the switching of the signal. The signals of each group are routed successively. This causes the signals of later groups to be routed between the signals of previous groups thereby providing shielding between signals lines of the same group.
    Type: Application
    Filed: May 9, 2012
    Publication date: November 14, 2013
    Applicant: LSI CORPORATION
    Inventor: Anuj Soni
  • Publication number: 20130219128
    Abstract: Methods and apparatus are provided for reusing snoop responses and data phase results in a bus controller. A bus controller receives an incoming bus transaction BTR1 corresponding to an incoming cache transaction CTR1 for an entry in at least one cache; issues a snoop request with a cache line address of the incoming bus transaction BTR1 for the entry to a plurality of cache controllers; collects at least one snoop response from the plurality of cache controllers; broadcasts a combined snoop response to the plurality of cache controllers, wherein the combined snoop response is a combination of the snoop responses from the plurality of cache controllers; and broadcasts cache line data from a source cache for the entry during a data phase to the plurality of cache controllers, wherein a subsequent cache transaction CTR2 for the entry is processed based on the broadcast combined snoop response and the broadcast cache line data.
    Type: Application
    Filed: February 21, 2012
    Publication date: August 22, 2013
    Inventors: Vidyalakshmi Rajagopalan, Archna Rai, Sharath Kashyap, Anuj Soni
  • Publication number: 20130219129
    Abstract: Methods and apparatus are provided for reusing snoop responses and data phase results in a cache controller. A cache controller receives a broadcast combined snoop response from a bus controller, wherein the broadcast combined snoop response corresponds to an incoming bus transaction BTR1 corresponding to a cache transaction CTR1 for an entry in at least one cache and wherein the combined snoop response is a combination of at least one snoop response from a plurality of cache controllers; receives broadcast cache line data from a source cache as instructed by the bus controller for the entry during a data phase; and processes a subsequent cache transaction CTR2 for the entry based on one or more of the broadcast combined snoop response and the broadcast cache line data.
    Type: Application
    Filed: February 21, 2012
    Publication date: August 22, 2013
    Inventors: Vidyalakshmi Rajagopalan, Archna Rai, Sharath Kashyap, Anuj Soni
  • Publication number: 20130103903
    Abstract: Methods and apparatus are provided for reusing prior tag search results in a cache controller. A cache controller is disclosed that receives an incoming request for an entry in the cache having a first tag; determines if there is an existing entry in a buffer associated with the cache having the first tag; and reuses a tag access result from the existing entry in the buffer having the first tag for the incoming request. An indicator can be maintained in the existing entry to indicate whether the tag access result should be retained. Tag access results can optionally be retained in the buffer after completion of a corresponding request. The tag access result can be reused by (i) reallocating the existing entry to the incoming request if the indicator in the existing entry indicates that the tag access result should be retained; and/or (ii) copying the tag access result from the existing entry to a buffer entry allocated to the incoming request if a hazard is detected.
    Type: Application
    Filed: October 20, 2011
    Publication date: April 25, 2013
    Inventors: Vidyalakshmi Rajagopalan, Archna Raj, Sharath Kashyap, Anuj Soni