Abstract: A method involves determining failure in time rate for a circuit. The method may include obtaining circuit data regarding a circuit. The circuit may include a first wire segment and a second wire segment. The method may further include obtaining reliability data. The reliability data may describe a failure of the circuit over a pre-determined time period. The method may further include obtaining a thermal map. The method may further include determining a first failure rate for the first wire segment of the circuit. The first failure rate may be a probability that the first wire segment fails in a predetermined amount of time. The method may further include determining a second failure rate for the second wire segment of the circuit. The method may further include generating a model of the circuit. The model of the circuit may describe the first and the second failure rate of the circuit.

Abstract: A method involves determining failure in time rate for a circuit. The method may include obtaining circuit data regarding a circuit. The circuit may include a first wire segment and a second wire segment. The method may further include obtaining reliability data. The reliability data may describe a failure of the circuit over a pre-determined time period. The method may further include obtaining a thermal map. The method may further include determining a first failure rate for the first wire segment of the circuit. The first failure rate may be a probability that the first wire segment fails in a predetermined amount of time. The method may further include determining a second failure rate for the second wire segment of the circuit. The method may further include generating a model of the circuit. The model of the circuit may describe the first and the second failure rate of the circuit.

Abstract: A method for visually merging design databases without generating a merged database of the design databases is disclosed. A first display window that is to display information from a particular database in non-overlay mode is assigned to the first stack position, and a second display window that is to display information from another database in overlay mode is assigned to a next stack position. The second display window is positioned relative to the first display window using position information received from the first display window via an inter-process communication channel.

Abstract: A method involves determining failure in time rate for a circuit. The method may include obtaining circuit data regarding a circuit. The circuit may include a first wire segment and a second wire segment. The method may further include obtaining reliability data. The reliability data may describe a failure of the circuit over a pre-determined time period. The method may further include obtaining a thermal map. The method may further include determining a first failure rate for the first wire segment of the circuit. The first failure rate may be a probability that the first wire segment fails in a predetermined amount of time. The method may further include determining a second failure rate for the second wire segment of the circuit. The method may further include generating a model of the circuit. The model of the circuit may describe the first and the second failure rate of the circuit.

Abstract: Techniques are provided for improving performance of spatial queries by defining a grid that divides the domain space into cells, and then using a cell-to-item mapping to determine which items do not have to be individually evaluated against the location criteria of the spatial queries. Based on the cell to which an item belongs, the item may automatically qualify as a match, be automatically disqualified, or require item-specific evaluation. To account for items with size, the query window of a spatial query may be expanded. To limit the degree to which the query window is expanded, a plurality of grids may be established for the domain space, where each grid has differently sized cells, and items are assigned to grids based on the size of the items.

Abstract: A method for visually merging design databases without generating a merged database of the design databases is disclosed. A first display window that is to display information from a particular database in non-overlay mode is assigned to the first stack position, and a second display window that is to display information from another database in overlay mode is assigned to a next stack position. The second display window is positioned relative to the first display window using position information received from the first display window via an inter-process communication channel.

Abstract: A method involves determining failure in time rate for a circuit. The method may include obtaining circuit data regarding a circuit. The circuit may include a first wire segment and a second wire segment. The method may further include obtaining reliability data. The reliability data may describe a failure of the circuit over a pre-determined time period. The method may further include obtaining a thermal map. The method may further include determining a first failure rate for the first wire segment of the circuit. The first failure rate may be a probability that the first wire segment fails in a predetermined amount of time. The method may further include determining a second failure rate for the second wire segment of the circuit. The method may further include generating a model of the circuit. The model of the circuit may describe the first and the second failure rate of the circuit.

Abstract: Techniques are provided for improving performance of spatial queries by defining a grid that divides the domain space into cells, and then using a cell-to-item mapping to determine which items do not have to be individually evaluated against the location criteria of the spatial queries. Based on the cell to which an item belongs, the item may automatically qualify as a match, be automatically disqualified, or require item-specific evaluation. To account for items with size, the query window of a spatial query may be expanded. To limit the degree to which the query window is expanded, a plurality of grids may be established for the domain space, where each grid has differently sized cells, and items are assigned to grids based on the size of the items.

Abstract: Techniques for modeling a circuit cell of a microprocessor or other integrated circuit for hierarchical powergrid analysis are disclosed herein. Distribution coefficients, used to distribute node voltages and capacitances to respective parts of the cell, are determined for each internal node of the cell. Current distribution coefficients may also be determined for each resistor in the cell. Using the distribution coefficients, internal cell capacitances are modeled as port capacitors. Resistive elements are modeled as a resistor network having no internal nodes. Transistor elements are modeled as port current sources. Such a model permits back calculation of internal node voltages and currents.

Abstract: Ports at which a cell served by a local powergrid is to be modeled are designated on a selected metal layer N-levels down from the topmost metal layer of the local powergrid. The cell is modeled at the designated ports, excluding any metal layers above the selected metal layer. Any metal layers of the local powergrid above the selected metal layer are included as part of a model of the global powergrid, rather than as part of the local powergrid, and a hierarchical powergrid analysis is performed.

Abstract: Methods of and apparatuses for performing electromigration risk analyses of power interconnect systems in integrated circuits employ a pseudo dynamic simulation model, whereby all transistor gates of a transistor network coupled to the power interconnect system are switched at the same time. To accomplish simultaneity in switching, a netlist characterizing the transistor network is altered in a manner that all gates are connected to a common input signal node. Time dependent currents drawn by transistors of the transistor network connected to the power interconnect system are determined. The time dependent currents and dimensional characteristics gleaned from the layout of the integrated circuit are used to calculate peak, average, or RMS current densities. The current densities are compared to electromigration rules to determine what areas of the power interconnect system may be in violation of the electromigration rules.

Abstract: Methods of and apparatuses for performing electromigration risk analyses of power interconnect systems in integrated circuits employ a pseudo dynamic simulation model, whereby all transistor gates of a transistor network coupled to the power interconnect system are switched at the same time. To accomplish simultaneity in switching, a netlist characterizing the transistor network is altered in a manner that all gates are connected to a common input signal node. Time dependent currents drawn by transistors of the transistor network connected to the power interconnect system are determined. The time dependent currents and dimensional characteristics gleaned from the layout of the integrated circuit are used to calculate peak, average, or RMS current densities. The current densities are compared to electromigration rules to determine what areas of the power interconnect system may be in violation of the electromigration rules.

Abstract: A method of circuit simulation of an overall circuit including at least one nonlinear component and a plurality of fixed linear components. The process begins by obtaining a netlist for the overall circuit. Next, one or more of the individual nonlinear components from the netlist are precharacterized. Generally the precharacterization is performed in advance of the circuit simulation and the results are stored in a table. The overall circuit is broken into one or more subcircuits. The number and size of the subcircuits will depend on the circumstances. The nonlinear components are substituted with equivalent linear components based on the precharacterization. A simulation matrix is built. Generally the matrix is carefully partitioned to reduce the number of calculations. A simulation is run for each of the subcircuits. Finally, the subcircuit simulations are combined to form the overall circuit simulation.