Abstract: A system comprises one or more slice-aggregated cryptographic slices each configured to perform a plurality of operations on an incoming data transfer at a first processing rate by aggregating one or more individual cryptographic slices each configured to perform the plurality of operations on a portion of the incoming data transfer at a second processing rate. Each of the individual cryptographic slices comprises in a serial connection an ingress block configured to take the portion of the incoming data transfer at the second processing rate, a cryptographic engine configured to perform the operations on the portion of the incoming data transfer, an egress block configured to process a signature of the portion and output the portion of the incoming data transfer once the operations have completed. The first processing rate of each slice-aggregated cryptographic slices equals aggregated second processing rates of the individual cryptographic slices in the slice-aggregated cryptographic slice.

Abstract: Embodiments disclosed are directed to methods for scheduling packets. According to example embodiments the method includes receiving, using a first layer in a communication protocol, a first request from a second layer in the communication protocol. The first request indicates to the first layer to output a data stream that includes a first location for the second layer to include a first control packet. The first layer is at a higher level of abstraction than the second layer. The method further includes transmitting, using the first layer, a first response to the second layer. The first response is based on the first request, and the first response identifies the first location in the data stream and a time of occurrence of the first location in the data stream.

Abstract: A system comprises one or more slice-aggregated cryptographic slices each configured to perform a plurality of operations on an incoming data transfer at a first processing rate by aggregating one or more individual cryptographic slices each configured to perform the plurality of operations on a portion of the incoming data transfer at a second processing rate. Each of the individual cryptographic slices comprises in a serial connection an ingress block configured to take the portion of the incoming data transfer at the second processing rate, a cryptographic engine configured to perform the operations on the portion of the incoming data transfer, an egress block configured to process a signature of the portion and output the portion of the incoming data transfer once the operations have completed. The first processing rate of each slice-aggregated cryptographic slices equals aggregated second processing rates of the individual cryptographic slices in the slice-aggregated cryptographic slice.

Abstract: A circuit arrangement includes an encryption circuit and a decryption circuit. A cryptographic shell circuit has a transmit channel and a receive channel in parallel with the transmit channel. The transmit channel includes an encryption interface circuit coupled to the encryption circuit. The encryption interface circuit determines first cryptographic parameters based on data in a plaintext input packet and inputs the first cryptographic parameters and plaintext input packet to the encryption circuit. The receive channel includes a decryption interface circuit coupled to the decryption circuit. The decryption interface circuit determines second cryptographic parameters based on data in a ciphertext input packet and inputs the second cryptographic parameters and ciphertext input packet to the decryption circuit.

Abstract: A circuit arrangement includes an encryption circuit and a decryption circuit. A cryptographic shell circuit has a transmit channel and a receive channel in parallel with the transmit channel. The transmit channel includes an encryption interface circuit coupled to the encryption circuit. The encryption interface circuit determines first cryptographic parameters based on data in a plaintext input packet and inputs the first cryptographic parameters and plaintext input packet to the encryption circuit. The receive channel includes a decryption interface circuit coupled to the decryption circuit. The decryption interface circuit determines second cryptographic parameters based on data in a ciphertext input packet and inputs the second cryptographic parameters and ciphertext input packet to the decryption circuit.

Abstract: An invention is provided for parallel ECC error location in a memory. The invention includes partitioning a set of field elements into w partitions. Then, for each of the w partitions of field elements, i) providing a set of r different field elements of the partition to r parallel search element. Next, in operation ii), each parallel search element computes a sum that is based on a set of coefficients of an error locator polynomial and the field element provided to the particular parallel search element. The set of field elements is advanced r field elements in GF(2m), and operations i) through iii) are repeated using the next r different field elements of the partition.

Abstract: In some embodiments a switching device is disclosed that includes one or more ingress queues to queue data received from external sources while waiting to forward the data to one or more egress queues. The egress queues queue the data while waiting to transmit the data to external sources. The switching device also includes a switch fabric to provide connectivity between the one or more ingress queues and the one or more egress queues. The switching device further includes an ingress flow-control manager to monitor flow-control state of the one or more ingress queues, and to detect and recover from loss of ON flow-control messages. Other embodiments are otherwise disclosed herein.

Abstract: An invention is provided for parallel ECC error location in a memory. The invention includes partitioning a set of field elements into w partitions. Then, for each of the w partitions of field elements, i) providing a set of r different field elements of the partition to r parallel search element. Next, in operation ii), each parallel search element computes a sum that is based on a set of coefficients of an error locator polynomial and the field element provided to the particular parallel search element. The set of field elements is advanced r field elements in GF(2m), and operations i) through iii) are repeated using the next r different field elements of the partition.

Abstract: In general, in one aspect, the disclosure describes a switching device that includes a plurality of ingress ports to receive data from external sources and a plurality of egress ports to transmit data to external destinations. The switching device also includes a plurality of queues to store data waiting to be transmitted from a particular ingress port to a particular egress port. A request generator generates requests for permission to transmit data for the queues. A request indicates a cumulative amount of data contained in a respective queue. A switching matrix provides selective connectivity between the ingress ports and the egress ports. The switching device further includes a scheduler to receive the requests, generate grants based thereon, and configure the switching matrix. The scheduler incorporates a mechanism to periodically monitor its operating efficiency and perturb its internal state when its efficiency is below a certain desired level.

Abstract: In general, in one aspect, the disclosure describes a multi-stage switch having at least one ingress switch module to receive data and to generate frames that are transmitted as a wavelength division multiplexed signal. The multi-stage switch further includes a core switch module operatively connected to receive the wavelength division multiplexed signal from the at least one ingress switch module and to switch the frames. The multi-stage switch additionally includes at least one egress switch module to receive the wavelength division multiplexed signal from the core switch module and to transmit data.

Abstract: In general, in one aspect, a switching device includes a plurality of ingress ports to receive data from external sources and a plurality of egress ports to transmit data to external destinations. The switching device also includes a plurality of queues to store data waiting to be transmitted from a particular ingress port to a particular egress port. A request generator generates requests for permission to transmit data for the queues. A request indicates a cumulative amount of data contained in a respective queue. A switching matrix provides selective connectivity between the ingress ports and the egress ports. The switching device further includes a scheduler to receive the requests, generate grants based thereon, and configure the switching matrix. The scheduler operates on a pipeline schedule and modifies the requests received to account for grants generated in current period or previous period not reflected in the queues.

Abstract: In general, in one aspect, the disclosure describes an apparatus capable of queuing and de-queuing data stored in a plurality of queues. The apparatus includes a status storage device to track status for each of the plurality of queues, a status cache to track status for a subset of the plurality of queues that are undergoing processing, and a queuing engine to queue incoming data and de-queue outgoing data. The queuing engine receives and updates the status for the subset of the plurality of queues from the status cache and receives and updates the status for remaining queues from the status storage device.

Abstract: In general, in one aspect, the disclosure describes a multi-stage switch having at least one ingress switch module to receive data and to generate frames that are transmitted as a wavelength division multiplexed signal. The multi-stage switch further includes a core switch module operatively connected to receive the wavelength division multiplexed signal from the at least one ingress switch module and to switch the frames. The multi-stage switch additionally includes at least one egress switch module to receive the wavelength division multiplexed signal from the core switch module and to transmit data. The at least one ingress switching module and the at least one egress switching module are capable of replicating multicast data packets.

Abstract: In general, in one aspect, the disclosure describes a multi-stage switch having a plurality of ingress switching modules to receive data and to generate frames that are transmitted as a wavelength division multiplexed signal. The multi-stage switch further includes a core switching module operatively connected to receive the wavelength division multiplexed signal from the at least one ingress switch module and to switch the frames. The multi-stage switch additionally includes a plurality of egress switching modules to receive the wavelength division multiplexed signal from the core switch module and to transmit data. The multi-stage switch is capable of detecting faulty paths and transmitting data through fault-free paths.

Abstract: In general, in one aspect, the disclosure describes an apparatus that includes a plurality of ingress modules to receive packets from external sources and to store the packets in queues based on flow. A plurality of egress modules transmit packets received from the plurality of ingress modules to external sources. A crossbar matrix provides configurable connectivity between the plurality of ingress modules and the plurality of egress modules. A scheduler receives requests for utilization of the crossbar matrix from at least a subset of the plurality of ingress modules, arbitrates amongst the requests, grants at least a subset of the requests, and configures the crossbar matrix based on the granted requests. The flows are assigned weights defining an amount of data to be transmitted during a period. When a flow meets or exceeds the assigned weight during the period the flow is deactivated from the schedule arbitration.

Abstract: In some embodiments a processing device is disclosed. The processing device is configured to read data from a memory device. The processing device transmits a read request to the memory device for a data block at a certain address and reads the data block for the certain address from the memory device. The processing device dynamically detects boundaries for the data block read by detecting an alignment pattern in data received from the memory device. Other embodiments are otherwise disclosed herein.

Abstract: In general, in one aspect, the disclosure describes a switching device that includes a plurality of ports. The ports operate at asymmetric speeds. The apparatus also includes a switching matrix to provide selective connectivity between the ports. The apparatus further includes a plurality of channels to connect the ports to the switching matrix. The number of channels associated with each port is determined by speed of the port.

Abstract: In general, in one aspect, a switching device is described that includes a segmentation unit to receive packets and divide packets having a length greater than a maximum segment length into multiple segments. A plurality of queues associated with a source and a destination stores the segments. A request generator generates requests that include external factors including amount of data contained in the queue and at least some subset of priority and age. A scheduler receives the requests and assigns the requests an internal priority based on the external factors. The scheduler processes the requests for the queues by internal priority in order to generate grants. A framer, responsive to the scheduler, aggregates a plurality of segments for the queues that received a grant to form a frame and to transmit the frame to an associated destination. The frame may contain segments associated with different packets.

Abstract: In general, in one aspect, the disclosure describes an apparatus that includes a transmission module to split a data segment into a plurality of data stripes and transmit each data stripe over an associated data channel. The plurality of data channels are organized into at least one group and each group has an associated parity channel to transmit a parity stripe generated based on the data stripes within the group. The apparatus also includes a reception module to receive the plurality of data stripes and the at least one parity stripe. The apparatus further includes a controller to control the operation of the apparatus.

Abstract: In some embodiments a processing device is disclosed. The processing device is configured to read data from a memory device. The processing device transmits a read request to the memory device for a data block at a certain address and reads the data block for the certain address from the memory device. The processing device dynamically detects boundaries for the data block read by detecting an alignment pattern in data received from the memory device. Other embodiments are otherwise disclosed herein.