Abstract: Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body; forming a source; forming an active region contact trench that extends through the source and the body into a drain; forming a Schottky barrier controlling layer in the epitaxial layer in bottom region of the active region contact trench; and disposing a contact electrode within the active region contact trench. The Schottky barrier controlling layer controls Schottky barrier height of a Schottky diode formed by the contact electrode and the drain.

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination.

Abstract: A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in the trenches that define the mesa. A second conductive region is formed in the portion of the trenches that define the mesa. The second conductive region is electrically isolated from the first conductive region by the intermediate dielectric region. A first electrical contact is made to the second conductive regions and a second electrical contact to the first conductive region in the shield electrode pickup trenches. One or more Schottky diodes are formed within the mesa.

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination.

Abstract: A corner layout for a semiconductor device that maximizes the breakdown voltage is disclosed. The device includes first and second subsets of the striped cell arrays. The ends of each striped cell in the first array is spaced a uniform distance from the nearest termination device structure. In the second subset, the ends of striped cells proximate a corner of the active cell region are configured to maximize breakdown voltage by spacing the ends of each striped cell a non-uniform distance from the nearest termination device structure. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type. A first conductivity type epitaxial layer disposed on a top surface of the substrate includes a surface shielded region above a less heavily doped voltage blocking region. A body region of a second conductivity type opposite the first conductivity type is disposed near a top surface of the surface shielded region. A first conductivity type source region is disposed near the top surface inside the body region. A drain is disposed at a bottom surface of the substrate. A gate overlaps portions of the source and body regions. Gate insulation separates the gate from the source and body regions. First and second trenches formed in the surface shielded region are lined with trench insulation material and filled with electrically conductive trench filling material. Second conductivity type buried doped regions are positioned below the first and second trenches, respectively.

Abstract: An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. Source and body regions inside the active region are at source potential and source and body regions outside the isolation trench are at drain potential. The device can be made using a three-mask or four-mask process.

Abstract: A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide. Methods for manufacturing such device are also disclosed. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: This invention discloses a method for manufacturing a semiconductor power device on a semiconductor substrate supporting a . drift region composed of an epitaxial layer. The method includes a first step of growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; a second step of applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; and a third step of repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers, each of which is implanted with the dopant regions of the alternating conductivity types.

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area wherein the edge termination area comprises a wide trench filled with a field-crowding reduction filler and a buried field plate buried under a top surface of the semiconductor substrate and laterally extended over a top portion of the field crowding field to move a peak electric field laterally away from the active cell area. In a specific embodiment, the field-crowding reduction filler comprises a silicon oxide filled in the wide trench.

Abstract: The present invention is directed to a lead-frame having a stack of semiconductor dies with interposed metalized clip structure. Level projections extend from the clip structure to ensure that the clip structure remains level during fabrication.

Abstract: The present disclosure describes a termination structure for a high voltage semiconductor transistor device. The termination structure is composed of at least two termination zones and an electrical disconnection between the body layer and the edge of the device. A first zone is configured to spread the electric field within the device. A second zone is configured to smoothly bring the electric field back up to the top surface of the device. The electrical disconnection prevents the device from short circuiting the edge of the device. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: Disclosed inventions are directed to advanced high-voltage switches with improved performance characteristics, increased reliability, and better compatibility with conventional gate drivers. The inventions disclosed herein implement a hybrid switch, comprising a high-voltage normally-on SiC VJFET, controlled via a low-voltage Si MOSFET in a cascode (Baliga-pair) configuration. The SiC VJFET and Si MOSFET are integrated monolithically at a wafer level, with the Si MOSFET fabricated on the Si layer that is directly adjacent to a dielectric layer on top of the SiC VJFET. Methods of making and operating these switches are also provided.

Abstract: A trench formed in a body layer and epitaxial layer of a substrate is lined with a dielectric layer. A shield electrode formed within a lower portion of the trench is insulated by the dielectric layer. A gate electrode formed in the trench above the shield electrode is insulated from the shield electrode by another dielectric layer. One or more source regions formed within the body layer is adjacent a sidewall of the trench. A source pad formed above the body layer is electrically connected to the source regions and insulated from the gate electrode and shield electrode. The source pad provides an external contact to the source region. A gate pad provides an external contact to the gate electrode. A shield electrode pad provides an external contact to the shield electrode. A resistive element is electrically connected between the shield electrode pad and a source lead.

Abstract: A semiconductor power device formed in a semiconductor substrate comprising a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region supported by a heavily doped region. The semiconductor power device further comprises source trenches opened into the highly doped region filled with conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises buried P-regions disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A circuit includes a vertical conduction gallium nitride-based Schottky diode and a vertical conduction silicon based PN junction diode connected in parallel. The Schottky diode and the PN junction diode are packaged in the same semiconductor package and the PN junction diode does not conduct in response to the Schottky diode being forward biased. In some embodiments, the silicon based PN junction diode has a breakdown voltage lower than a breakdown voltage of the gallium nitride-based Schottky diode. The silicon based PN junction diode enters breakdown in response to the gallium nitride-based Schottky diode being reverse biased to divert a reverse bias avalanche current away from the gallium nitride-based Schottky diode.

Abstract: A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW.

Abstract: This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.

Abstract: This invention discloses a semiconductor power device formed in a semiconductor substrate. The semiconductor power device further includes a channel stop region near a peripheral of the semiconductor substrate wherein the channel stop region further includes a peripheral terminal of a diode corresponding with another terminal of the diode laterally opposite from the peripheral terminal disposed on an active area of the semiconductor power device. In an embodiment of this invention, the semiconductor power device is an insulated gate bipolar transistor (IGBT).

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area wherein the edge termination area comprises a wide trench filled with a field-crowding reduction filler and a buried field plate buried under a top surface of the semiconductor substrate and laterally extended over a top portion of the field crowding field to move a peak electric field laterally away from the active cell area. In a specific embodiment, the field-crowding reduction filler comprises a silicon oxide filled in the wide trench.