Patents by Inventor Anup Hosangadi

Anup Hosangadi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10747502
    Abstract: Circuits and method for multiplying floating point operands. An exponent adder circuit sums a first exponent and a second exponent and generates an output exponent. A mantissa multiplier circuit multiplies a first mantissa and a second mantissa and generates an output mantissa. A first conversion circuit converts the output exponent and output mantissa into a fixed point number. An accumulator circuit sums contents of an accumulation register and the fixed point number into an accumulated value and stores the accumulated value in the accumulation register.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: August 18, 2020
    Assignee: Xilinx, Inc.
    Inventors: Satyaprakash Pareek, Anup Hosangadi, Bing Tian, Ashish Sirasao, Yao Fu, Oscar Fernando C. Fernandez, Michael Wu, Christopher H. Dick
  • Publication number: 20200089472
    Abstract: Circuits and method for multiplying floating point operands. An exponent adder circuit sums a first exponent and a second exponent and generates an output exponent. A mantissa multiplier circuit multiplies a first mantissa and a second mantissa and generates an output mantissa. A first conversion circuit converts the output exponent and output mantissa into a fixed point number. An accumulator circuit sums contents of an accumulation register and the fixed point number into an accumulated value and stores the accumulated value in the accumulation register.
    Type: Application
    Filed: September 19, 2018
    Publication date: March 19, 2020
    Applicant: Xilinx, Inc.
    Inventors: Satyaprakash Pareek, Anup Hosangadi, Bing Tian, Ashish Sirasao, Yao Fu, Oscar Fernando C. Fernandez, Michael Wu, Christopher H. Dick
  • Patent number: 10534885
    Abstract: Range information is determined for each variable of a circuit design. The range information is propagated from inputs to outputs of nodes of a DFG representation of the circuit design. For each multiplexer of the circuit design represented as a multiplexer node in the DFG, whether range information associated with a selector input of the multiplexer node restricts selection of data inputs of the multiplexer node to only one selected data input of the multiplexer node is determined. In response to determining that range information associated with the selector input restricts selection of data inputs to only one data input, the DFG is modified by connecting the selected data input to each load of the multiplexer node, and removing the multiplexer node, a corresponding select logic node of the multiplexer node, and nodes connected to unselected data inputs of the multiplexer node.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: January 14, 2020
    Assignee: XILINX, INC.
    Inventors: Sumanta Datta, Anup Hosangadi, Aman Gayasen
  • Patent number: 10331836
    Abstract: Implementing a circuit design can include determining a chain of a plurality of loop elements of a circuit design, wherein each loop element includes a bit select node configured to perform a bit assignment operation and a corresponding address calculation node, wherein the address calculation nodes use a common variable to calculate a starting bit location provided to the corresponding bit select node. In response to the determining, the chain is replicated resulting in one chain for each value of the common variable and transforming each chain into a plurality of wires. A multiplexer is inserted into the circuit design. The plurality of wires for each chain is coupled to inputs of the multiplexer and the common variable is provided to the multiplexer as a select signal.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: June 25, 2019
    Assignee: XILINX, INC.
    Inventors: Anup Hosangadi, Sumanta Datta, Aman Gayasen, Ashish Sirasao
  • Patent number: 7895420
    Abstract: A method for reducing operations in a processing environment is provided that includes generating one or more binary representations, one or more of the binary representations being included in one or more linear equations that include one or more operations. The method also includes converting one or more of the linear equations to one or more polynomials and then performing kernel extraction and optimization on one or more of the polynomials. One or more common subexpressions associated with the polynomials are identified in order to reduce one or more of the operations.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: February 22, 2011
    Assignee: Fujitsu Limited
    Inventors: Farzan Fallah, Anup Hosangadi, Ryan C. Kastner
  • Publication number: 20070180010
    Abstract: A method for reducing operations in a processing environment is provided that includes generating one or more binary representations. One or more of the binary representations are included in one or more linear equations that include one or more operations. The method also includes converting one or more of the linear equations to one or more polynomials and identifying one or more common subexpressions associated with the polynomials in order to reduce one or more of the operations. The identifying step is facilitated by an algorithm that iteratively selects divisors and then uses the divisors to eliminate common subexpressions among the linear equations. The method can also take into account the delay of expressions while performing the optimization. Further, it can optimize a polynomial to reduce the number of operations. Additionally, it can optimize the exponents of variables.
    Type: Application
    Filed: January 13, 2006
    Publication date: August 2, 2007
    Applicants: University of California
    Inventors: Farzan Fallah, Anup Hosangadi, Ryan Kastner
  • Publication number: 20060294169
    Abstract: A method for reducing operations in a processing environment is provided that includes generating one or more binary representations, one or more of the binary representations being included in one or more linear equations that include one or more operations. The method also includes converting one or more of the linear equations to one or more polynomials and then performing kernel extraction and optimization on one or more of the polynomials. One or more common subexpressions associated with the polynomials are identified in order to reduce one or more of the operations.
    Type: Application
    Filed: February 25, 2005
    Publication date: December 28, 2006
    Inventors: Farzan Fallah, Anup Hosangadi, Ryan Kastner