Patents by Inventor Anup J. DEKA

Anup J. DEKA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11742754
    Abstract: A one-shot inductor current scheme which includes a controller to generate a signal to control a high-side switch and a low-side switch such that the high-side switch remains turned on beyond a turn-on time if a voltage level on an output supply rail remains below a reference. The scheme reduces the minimum operating voltage Vmin and/or frequency guard-band of the SoCs (system-on-chips).
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: August 29, 2023
    Assignee: Intel Corporation
    Inventors: Anup J Deka, Shobhit Tyagi, Sudhir Polarouthu, Biranchinath Sahu
  • Publication number: 20210124382
    Abstract: A one-shot inductor current scheme which includes a controller to generate a signal to control a high-side switch and a low-side switch such that the high-side switch remains turned on beyond a turn-on time if a voltage level on an output supply rail remains below a reference. The scheme reduces the minimum operating voltage Vmin and/or frequency guard-band of the SoCs (system-on-chips).
    Type: Application
    Filed: October 13, 2020
    Publication date: April 29, 2021
    Applicant: Intel Corporation
    Inventors: Anup J. Deka, Shobhit Tyagi, Sudhir Polarouthu, Biranchinath Sahu
  • Patent number: 10911269
    Abstract: An apparatus is described. The apparatus includes a decision feedback equalizer circuit having a summation circuit. The summation circuit has a differential pair that includes first and second transistors coupled to a current source. The current source is to draw a current through the first and second transistors. The decision feedback circuit also includes a circuit to adjust the current to compensate for a change in electron mobility of at least one transistor of the current source.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Anup J. Deka, Kambiz R. Munshi
  • Publication number: 20190013973
    Abstract: An apparatus is described. The apparatus includes a decision feedback equalizer circuit having a summation circuit. The summation circuit has a differential pair that includes first and second transistors coupled to a current source. The current source is to draw a current through the first and second transistors. The decision feedback circuit also includes a circuit to adjust the current to compensate for a change in electron mobility of at least one transistor of the current source.
    Type: Application
    Filed: July 6, 2017
    Publication date: January 10, 2019
    Inventors: Anup J. DEKA, Kambiz R. MUNSHI