Patents by Inventor Anup Nayak

Anup Nayak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190317582
    Abstract: A device includes a USB-C controller instantiated as a first integrated circuit that includes a first set of host terminals coupled to host controllers and a second set of terminals coupled to sets of D+/D? terminals of a type-C receptacle. A D+/D? multiplexer is to selectively couple the first set of host terminals to the second set of terminals. An electrostatic discharge (ESD) protection circuit is coupled between the D+/D? multiplexer and the second set of terminals. A charger detector circuit is coupled between a positive data system terminal and a negative data system terminal of the first set of terminals, the charger detector circuit to detect whether the second set of terminals is coupled to a USB charger through the type-C receptacle.
    Type: Application
    Filed: April 11, 2019
    Publication date: October 17, 2019
    Applicant: Cypress Semiconductor Corporation
    Inventors: Anup Nayak, Karri Rajesh, Hemant P. Vispute, Arun Khamesra
  • Publication number: 20190294226
    Abstract: A device and method that include a power control analog subsystem of a universal serial bus (USB) compatible power supply device is disclosed. The power control analog subsystem includes a programmable reference generator to generate first reference voltages. The power control analog subsystem also includes multiplexers, where each of a plurality of multiplexers are coupled to a first terminal and a second terminal of a producer field-effect transistor (FET) to receive a first voltage (Vbus_in) and a second voltage (Vbus_c) and to output second reference voltages. The power control analog subsystem further includes comparators, wherein each of the comparators is coupled to receive a corresponding reference voltage of the first reference voltages from the programmable reference generator and to receive a corresponding selected voltage from a corresponding multiplexer of the multiplexers. Each of the comparators is configured to output a corresponding system interrupt based on a corresponding voltage condition.
    Type: Application
    Filed: February 15, 2019
    Publication date: September 26, 2019
    Applicant: Cypress Semiconductor Corporation
    Inventors: Derwin W. Mattos, Anup Nayak
  • Publication number: 20190288532
    Abstract: Techniques for control of power switches in a USB Power Delivery (USB-PD) system are described herein. In an example embodiment, an integrated circuit comprises a programmable gate control circuit coupled to a provider field effect transistor (FET) and a consumer FET to provide control signals to the provider and consumer FETs in response to system conditions and application requirements of the USB-PD system. A pulldown current control circuit may provide additional control to slew rate for the slow turn-ON of provider and consumer FETs.
    Type: Application
    Filed: May 18, 2018
    Publication date: September 19, 2019
    Applicant: Cypress Semiconductor Corporation
    Inventors: Derwin Mattos, Hamid Khodabandehlou, Sumeet Gupta, Syed Raza, Anup Nayak
  • Publication number: 20190278360
    Abstract: Techniques for power-Field Effect Transistor (power-FET) gate drivers are described herein. In an example embodiment, a method for an USB-enabled system with an integrated circuit (IC) controller comprises: determining, by the IC controller, whether a first power path or a second power path is coupled to the IC controller, where the first power path comprises an external N-channel power-FET and the second power path comprises an external P-channel power-FET; turning and maintaining ON the external N-channel power-FET by the IC controller, when the first power path is determined as being coupled to the IC controller; and turning OFF the external N-channel power-FET and turning and maintaining ON the external P-channel power-FET by the IC controller, when the second power path is determined as being coupled to the IC controller.
    Type: Application
    Filed: March 6, 2019
    Publication date: September 12, 2019
    Applicant: Cypress Semiconductor Corporation
    Inventors: Anup Nayak, Ramakrishna Venigalla
  • Publication number: 20190278731
    Abstract: Techniques for voltage discharge from a USB Power Delivery (USB-PD) VBUS line are described herein. In an example embodiment, an integrated circuit comprises a discharge control logic coupled to a first discharge circuit and to a second discharge circuit. The first discharge circuit configured to couple to a power source node on the VBUS line. The second discharge circuit configured to couple to an output node on the VBUS line. The discharge control logic is configured to independently control the first discharge circuit and the second discharge circuit to discharge the voltage on the VBUS line.
    Type: Application
    Filed: May 18, 2018
    Publication date: September 12, 2019
    Applicant: Cypress Semiconductor Corporation
    Inventors: Derwin Mattos, Godwin Gerald Arulappan, Syed Raza, Anup Nayak, Sumeet Gupta, Venkat Mandagulathur
  • Patent number: 10353853
    Abstract: A device includes a USB-C controller instantiated as a first integrated circuit, the USB-C controller comprising a first pair of terminals to communicate with a first communication protocol that is other than USB, a second pair of terminals to communicate with a second communication protocol that is other than USB, and a third pair of terminals, each of which is to be coupled to a corresponding SBU1 terminal or SBU2 terminal of a type-C receptacle. The controller further includes a multiplexer to selectively couple the first pair of terminals to the third pair of terminals and the second pair of terminals to the third pair of terminals. The controller further includes a series of cascaded, low-voltage n-type field-effect transistors (LVNFETs) coupled between the multiplexer and each terminal of the third pair of terminals.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: July 16, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Arun Khamesra, Anup Nayak, Partha Mondal, Hemant P. Vispute, Ravi Konduru
  • Patent number: 10338656
    Abstract: A device includes a USB-C controller instantiated as a first integrated circuit that includes a first set of host terminals coupled to host controllers and a second set of terminals coupled to sets of D+/D? terminals of a type-C receptacle. A D+/D? multiplexer is to selectively couple the first set of host terminals to the second set of terminals. An electrostatic discharge (ESD) protection circuit is coupled between the D+/D? multiplexer and the second set of terminals. A charger detector circuit is coupled between a positive data system terminal and a negative data system terminal of the first set of terminals, the charger detector circuit to detect whether the second set of terminals is coupled to a USB charger through the type-C receptacle.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: July 2, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Anup Nayak, Karri Rajesh, Hemant Prakash Vispute, Arun Khamesra
  • Patent number: 10254820
    Abstract: Techniques for power Field Effect Transistor (power-FET) gate drivers are described herein. In an example embodiment, a USB-enabled system comprises a first and second power paths and an IC controller coupled to control the first and second power paths, where the first and second power paths are external to the IC controller and the IC controller is configured to operate both an N-channel power-FET in the first power path and a P-channel power-FET in the second power path.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: April 9, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Anup Nayak, Ramakrishna Venigalla
  • Patent number: 10228742
    Abstract: A device and method that include a power control analog subsystem of a universal serial bus (USB) compatible power supply device is disclosed. The power control analog subsystem includes a programmable reference generator to generate first reference voltages. The power control analog subsystem also includes multiplexers, where each of a plurality of multiplexers are coupled to a first terminal and a second terminal of a producer field-effect transistor (FET) to receive a first voltage (Vbus_in) and a second voltage (Vbus_c) and to output second reference voltages. The power control analog subsystem further includes comparators, wherein each of the comparators is coupled to receive a corresponding reference voltage of the first reference voltages from the programmable reference generator and to receive a corresponding selected voltage from a corresponding multiplexer of the multiplexers. Each of the comparators is configured to output a corresponding system interrupt based on a corresponding voltage condition.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: March 12, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Derwin W. Mattos, Anup Nayak
  • Publication number: 20180335818
    Abstract: A device and method that include a power control analog subsystem of a universal serial bus (USB) compatible power supply device is disclosed. The power control analog subsystem includes a programmable reference generator to generate first reference voltages. The power control analog subsystem also includes multiplexers, where each of a plurality of multiplexers are coupled to a first terminal and a second terminal of a producer field-effect transistor (FET) to receive a first voltage (Vbus_in) and a second voltage (Vbus_c) and to output second reference voltages. The power control analog subsystem further includes comparators, wherein each of the comparators is coupled to receive a corresponding reference voltage of the first reference voltages from the programmable reference generator and to receive a corresponding selected voltage from a corresponding multiplexer of the multiplexers. Each of the comparators is configured to output a corresponding system interrupt based on a corresponding voltage condition.
    Type: Application
    Filed: December 20, 2017
    Publication date: November 22, 2018
    Applicant: Cypress Semiconductor Corporation
    Inventors: Derwin W. Mattos, Anup Nayak
  • Publication number: 20170351320
    Abstract: Techniques for power Field Effect Transistor (power-FET) gate drivers are described herein. In an example embodiment, a USB-enabled system comprises a first and second power paths and an IC controller coupled to control the first and second power paths, where the first and second power paths are external to the IC controller and the IC controller is configured to operate both an N-channel power-FET in the first power path and a P-channel power-FET in the second power path.
    Type: Application
    Filed: July 12, 2017
    Publication date: December 7, 2017
    Applicant: Cypress Semiconductor Corporation
    Inventors: Anup Nayak, Ramakrishna Venigalla
  • Patent number: 9727123
    Abstract: Techniques for power Field Effect Transistor (power-FET) gate drivers are described herein. In an example embodiment, a device comprises a Universal Serial Bus (USB) subsystem that is disposed in a monolithic integrated circuit (IC). The USB subsystem comprises a gate-driver circuit configured to selectively control an external N-channel power-FET or an external P-channel power-FET.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: August 8, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Anup Nayak, Ramakrishna Venigalla
  • Patent number: 9122288
    Abstract: USB physical interface subsystems are provided that include a protection circuit including a power supply interface and a plurality of pin interfaces, a pin identifier circuit in communication with the protection circuit for detecting a device coupling to a pin connected to one pin interface of the plurality of pin interfaces, a USB physical interface, and a dual power supply regulator configured to receive power via the power supply interface, to continuously supply a first voltage to the protection circuit, and to provide a second voltage and a third voltage to the pin identifier circuit and the USB physical interface, the second voltage and the third voltage being switched outputs.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: September 1, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Anup Nayak, Nicholas Bodnaruk, Derwin Mattos, Shailja Garg
  • Patent number: 8090894
    Abstract: A controller circuit can provide communication paths between multiple host devices and at least one function interface (I/F), where a function I/F can allow access to a predetermined circuit function. The controller circuit can include an endpoint buffer circuit having a plurality of storage locations configurable as endpoints according to a predetermined data transmission protocol and a data switching circuit coupled to the endpoint point buffer circuit. The data switching circuit is configurable to provide communication paths that enable a first host I/F and a second host I/F to access at least a same function I/F, and enable the first and second host I/Fs to communicate with one another.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: January 3, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: Hamid Khodabandehlou, Syed Babar Raza, Anup Nayak
  • Patent number: 8074086
    Abstract: Disclosed are a circuit and a method for controlling dynamic in-rush current in a power management circuit. The circuit includes a current limiting unit having a first quantity of sleep mode devices. A voltage drop minimization unit is coupled to the current limiting unit and has a second quantity of sleep mode devices. The second quantity of sleep mode devices is greater than the first quantity of sleep mode devices. A sequential enabling unit is coupled to both the current limiting unit and the voltage drop minimization unit. The sequential enabling unit is configured to turn on the voltage drop minimization unit after the current limiting unit in accordance with a predetermined delay.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: December 6, 2011
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sanjay Kumar Sancheti, Anup Nayak, Bo Gao
  • Patent number: 7863971
    Abstract: A configurable power controller and method for controlling power of a macro circuit block, such as a memory circuit, in multiple power modes is described to help minimize power consumption of the macro circuit block when the application environment for the macro circuit block is in a lower power mode than during its normal power mode.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: January 4, 2011
    Assignee: Cypress Semiconductor Corporation
    Inventors: Anup Nayak, Sanjay Kumar Sancheti, Shailja Garg
  • Patent number: 7343510
    Abstract: A clock detection and selection circuit (100) can include a first counter (102-0) that generates a first count value CNT1 according to a first clock signal CLK1 and a second counter (102-1) that generates a second count value CNT2 according to a second clock signal CLK2. First separation-detect logic (102-0) and second separation-detect logic (102-1) determine if a pre-specified difference exists between a first count value (CNT1/CNT1?) and second count value (CNT2/CNT2?). According to such determinations, separation information (INF—1 and INF—2) can be generated indicating which clock signal (CLK1 or CLK2) is faster. Selection logic (106) can select a faster of the clock signals (CLK1 or CLK2) if the separation information values confirm one another.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: March 11, 2008
    Assignee: Cypress Semiconductor Corporation
    Inventors: Mark Ross, S. Babar Raza, Dimitris Pantelakis, Anup Nayak, Walter Bridgewater
  • Patent number: 7225283
    Abstract: An arbiter circuit (100) can include a latch (106) that latches competing input signals (Req_A and Req_B) to generate latch output signals (latn1 and latn2). A filter section (108) can prevent metastable states of latch output signals (latn1 and latn2) from propagating through to output signals (Sel_A and Sel_B). If both input signals (Req_A and Req_B) are activated, a feedback circuit (110) can activate a feedback signal (fb) after a predetermined delay (?), provided both output signals (Sel_A and Sel_B) remain inactive.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: May 29, 2007
    Assignee: Cypress Semiconductor Corporation
    Inventors: Anup Nayak, Dimitris Pantelakis, Fariborz Golshani, Derwin Mattos
  • Patent number: 7184359
    Abstract: A memory device, apparatus and method are provided for accessing memory cells. The device, apparatus, and method allow two or more electronic subsystems with corresponding external ports to access a single array of memory elements via a single internal port. Address, data, and control signals from each of the external ports are multiplexed onto the word line drivers and de-multiplexed from the sense amplifiers. Multiplexing and de-multiplexing operations are sequenced based on a state machine that receives synchronized signals from the external port. The synchronized signal can be clock signals that are synchronized to a high-speed sampling clock. Synchronization and sequencing functions can occur over a relatively few number of cycles of the high-speed sampling clock to minimize the time for resolving access conflicts, thereby maximizing the number of external ports which can access the internal port of the array.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: February 27, 2007
    Assignee: Cypress Semiconductor Corp.
    Inventors: Walter F. Bridgewater, Anup Nayak, Dimitris C. Pantelakis, S. Babar Raza
  • Patent number: 6922820
    Abstract: An apparatus comprising a circuit configured to select one of a number of identification (ID) codes in response to a voltage level at one or more pins.
    Type: Grant
    Filed: October 12, 2000
    Date of Patent: July 26, 2005
    Assignee: Cypress Semiconductor Corp.
    Inventors: Navaz Lulla, Anup Nayak