Abstract: A semiconductor device includes a first substrate that has a sensing portion that detects predetermined information, a second substrate that has a first processing portion that processes data supplied thereto from the sensing portion, and a third substrate having a second processing portion that processes data supplied thereto either from the first substrate or from the second substrate.

Abstract: The invention includes compositions, methods and kits for the in vivo identification of an enzyme that binds to a substrate. The invention comprises, in part, a photoreactive moiety to aid in identification of such an enzyme.

Abstract: Devices and methods for obtaining image data that preserves highlight details and shadow details from image data from a high dynamic range (HDR) image sensor are provided. For example, an image signal processor may include a first data path of a relatively high bit depth, front-end image processing logic, and a second data path of a relatively low bit depth. The first data path may receive HDR image data from an image sensor. The front-end image processing logic may convert the HDR image data into lower-bit-depth image data, while preserving highlight details and/or shadow details of the HDR image, by using at least two transfer functions that preserve different subsets of the high dynamic range. The second data path may output this lower-bit-depth image data to other image processing logic for additional image processing.

Abstract: An electronic device may be provided with an image sensor for capturing digital images. The image sensor may be used as part of image-sensor-based ambient light sensing circuitry for producing ambient light sensor readings. The image-sensor-based ambient light sensing circuitry may include a reference array. The reference array may be formed from an array of light sensor elements that are matched to elements in the image sensor but that are covered with a light blocking material. Control circuitry can measure current flow into the reference array and the image sensor array and can use current measurements from these arrays in producing a calibrated ambient light sensor reading. The control circuitry may make current measurements by measuring a decay time associated with the voltage of a discharging capacitor. A comparator, pulse generator, and switch may be used in periodically recharging the capacitor. The capacitor may be adjusted to ensure accurate readings.

Abstract: A semiconductor device includes a first substrate that has a sensing portion that detects predetermined information, a second substrate that has a first processing portion that processes data supplied thereto from the sensing portion, and a third substrate having a second processing portion that processes data supplied thereto either from the first substrate or from the second substrate.

Abstract: An electronic device may be provided with an image sensor for capturing digital images. The image sensor may be used as part of image-sensor-based ambient light sensing circuitry for producing ambient light sensor readings. The image-sensor-based ambient light sensing circuitry may include a reference array. The reference array may be formed from an array of light sensor elements that are matched to elements in the image sensor but that are covered with a light blocking material. Control circuitry can measure current flow into the reference array and the image sensor array and can use current measurements from these arrays in producing a calibrated ambient light sensor reading. The control circuitry may make current measurements by measuring a decay time associated with the voltage of a discharging capacitor. A comparator, pulse generator, and switch may be used in periodically recharging the capacitor. The capacitor may be adjusted to ensure accurate readings.

Abstract: Electronic devices and equipment may communicate over a wired communications path. The wired communications path may include one or more wires and may be associated with a headphone cable. Data may be conveyed in the form of a digital data stream containing multiple traffic channels. The digital data stream may include superframes, each of which has multiple frames of data. The frames of data may each contain a number of data slots. Some of the slots in a superframe may be used exclusively by a particular one of the traffic channels. Boundary slots may be shared between traffic channels. Data interface circuitry may implement a data dispersion algorithm that determines the pattern in which data from each traffic channel is distributed within each boundary slot. Transmitting data interface circuitry may merge traffic channels into a single data stream. Receiving data interface circuitry may reconstruct the traffic channels.

Abstract: The invention includes compositions, methods and kits for the in vivo identification of an enzyme that binds to a substrate. The invention comprises, in part, a photoreactive moiety to aid in identification of such an enzyme.

Abstract: Devices and methods for obtaining image data that preserves highlight details and shadow details from image data from a high dynamic range (HDR) image sensor are provided. For example, an image signal processor may include a first data path of a relatively high bit depth, front-end image processing logic, and a second data path of a relatively low bit depth. The first data path may receive HDR image data from an image sensor. The front-end image processing logic may convert the HDR image data into lower-bit-depth image data, while preserving highlight details and/or shadow details of the HDR image, by using at least two transfer functions that preserve different subsets of the high dynamic range. The second data path may output this lower-bit-depth image data to other image processing logic for additional image processing.

Abstract: Electronic devices and equipment may communicate over a wired communications path. The wired communications path may include one or more wires and may be associated with a headphone cable. Data may be conveyed in the form of a digital data stream containing multiple traffic channels. The digital data stream may include superframes, each of which has multiple frames of data. The frames of data may each contain a number of data slots. Some of the slots in a superframe may be used exclusively by a particular one of the traffic channels. Boundary slots may be shared between traffic channels. Data interface circuitry may implement a data dispersion algorithm that determines the pattern in which data from each traffic channel is distributed within each boundary slot. Transmitting data interface circuitry may merge traffic channels into a single data stream. Receiving data interface circuitry may reconstruct the traffic channels.

Abstract: Electronic devices and equipment may communicate over a wired communications path. The wired communications path may include one or more wires and may be associated with a headphone cable. Data may be conveyed in the form of a digital data stream containing multiple traffic channels. The digital data stream may include superframes, each of which has multiple frames of data. The frames of data may each contain a number of data slots. Some of the slots in a superframe may be used exclusively by a particular one of the traffic channels. Boundary slots may be shared between traffic channels. Data interface circuitry may implement a data dispersion algorithm that determines the pattern in which data from each traffic channel is distributed within each boundary slot. Transmitting data interface circuitry may merge traffic channels into a single data stream. Receiving data interface circuitry may reconstruct the traffic channels.

Abstract: Systems and methods for selecting and setting clock frequencies for an electronic device are disclosed. Specifically, clock frequencies may be adjusted to avoid interference with input electromagnetic energy, often in radio frequency bands. Clock frequencies may be chosen to minimize signal interference and improve device performance. In some embodiments, clock frequency information is stored in one or more lookup tables in device memory. In certain embodiments, a system processor can access the information stored in the lookup table and instruct system circuitry to adjust clock frequency as needed based on lookup table entries.

Abstract: Electronic devices and equipment may communicate over a wired communications path. The wired communications path may include one or more wires and may be associated with a headphone cable. Data may be conveyed in the form of a digital data stream containing multiple traffic channels. The digital data stream may include superframes, each of which has multiple frames of data. The frames of data may each contain a number of data slots. Some of the slots in a superframe may be used exclusively by a particular one of the traffic channels. Boundary slots may be shared between traffic channels. Data interface circuitry may implement a data dispersion algorithm that determines the pattern in which data from each traffic channel is distributed within each boundary slot. Transmitting data interface circuitry may merge traffic channels into a single data stream. Receiving data interface circuitry may reconstruct the traffic channels.

Abstract: Methods of identifying, designing and synthesizing uniquely targeting siRNA nucleotide sequences for a target mRNA sequence of a target species are disclosed. Methods of identifying, designing and synthesizing miRNA nucleotide sequences that does not function as a siRNA nucleotide sequence for mRNA of a target species are disclosed. Method of inhibiting expression of a target mRNA molecule are disclosed sequence. siRNA molecules including uniquely targeting siRNA molecules and RISCs comprising the same are disclosed. miRNA molecules that do not function as siRNA nucleotide sequences for mRNA of a target species are disclosed.

Abstract: Variable-length packets transmitted over a serial link do not have packet-start fields or unique symbols to mark the beginning of each packet. Instead, a length field indicates the packet's length, allowing the end of the packet to be located. Packets also do not have sequence numbers. When an error is detected, the receiver sends a control symbol over a reverse channel to signal the transmitter. The control symbol never occurs in a normal packet. Packet buffers in the transmitter and receiver have read and write pointers and also have de-allocation pointers that are synchronized between receiver and transmitter. As packets are error checked, the receiver advances its de-allocation pointer and updates the transmitter's de-allocation pointer, allowing the packets to be discarded from the transmitter's buffer only after the receiver finishes error checking. The transmitter re-transmits packets from its buffer starting from the de-allocation pointer when its receives the control symbol.

Abstract: A method and apparatus for determining clock insertion delays for a microprocessor design having a grid-based clock distribution. The method includes partitioning the complete clock net into a global clock net and a plurality of local clock nets, simulating a load for each of the local clock nets, simulating the global clock net, and combining the simulations to form the complete clock net. The method may further include evaluating the combination to determine whether the results converge and storing the simulation results in a Clock Data Model. When the results do not converge, the method re-simulates at least one of the local clock nets and re-simulates the global clock net. The Clock Data Model collects, manages, retrieves, and queries all of the simulation information. The method may further analyze the complete clock net to predict the clock skew for a given data transfer path for potential redesign.

Abstract: An apparatus and method for forming a Bragg grating on an optical fiber using a phase mask to diffract a beam of coherent energy and a lens combined with a pair of mirrors to produce two symmetrical virtual point sources of coherent energy in the plane of the optical fiber. The two virtual light sources produce an interference pattern along the optical fiber. In a further embodiment, the period of the pattern and therefore the Bragg wavelength grating applied to the fiber is varied with the position of the optical fiber relative the lens.

Abstract: A microchip configured to reliably transmit data is provided. The microchip includes a memory region and a selection module configured to select a portion of the data from the memory region. An error checking module configured to calculate a value derived from the selected portion of the data is provided. A pointer region including a plurality of object pointers is included. One of the object pointers is associated with an address of the portion of the data. The object pointer associated with the address is configured to receive a signal indicating an error associated with the transmission of the data. A scheduler module in communication with each of the plurality of object pointers is provided. The scheduler module is configured to schedule re-transmission of the selected portion of the data. A system and a method for reliably transmitting data between microchips are also provided.

Abstract: A method and apparatus for determining clock insertion delays for a microprocessor design having a grid-based clock distribution. The method includes partitioning the complete clock net into a global clock net and a plurality of local clock nets, simulating a load for each of the local clock nets, simulating the global clock net, and combining the simulations to form the complete clock net. The method may further include evaluating the combination to determine whether the results converge and storing the simulation results in a Clock Data Model. When the results do not converge, the method re-simulates at least one of the local clock nets and re-simulates the global clock net. The Clock Data Model collects, manages, retrieves, and queries all of the simulation information. The method may further analyze the complete clock net to predict the clock skew for a given data transfer path for potential redesign.

Abstract: A multiprocessor system includes a plurality of central processing units (CPUs) connected to one another by a system bus. Each CPU includes a cache controller to communicate with its cache, and a primary memory controller to communicate with its primary memory. When there is a cache miss in a CPU, the cache controller routes an address request for primary memory directly to the primary memory via the CPU as a speculative request without access the system bus, and also issues the address request to the system bus to facilitate data coherency. The speculative request is queued in the primary memory controller, which in turn retrieves speculative data from a specified primary memory address. The CPU monitors the system bus for a subsequent transaction that requests the specified data in the primary memory. If the subsequent transaction requesting the specified data is a read transaction that corresponds to the speculative address request, the speculative request is validated and becomes non-speculative.