Patents by Inventor Anupam Mohanty

Anupam Mohanty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Commands scheduled for frequency mismatch bubbles
    Patent number: 8069327
    Abstract: In some embodiments, a chip includes chip interface transmitters, a chip, and clock gearing logic. The transmitters are to transmit signals in frames including slots. The scheduler is to schedule signals at a first frequency including commands for first slots of the frames in general and commands for second slots of at least some frames immediately preceding frequency mismatch bubbles occurring when the frames are at a second frequency. The clock gearing logic is to provide the signals having the first frequency from the scheduler to the transmitters at the second frequency. Other embodiments are described.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: November 29, 2011
    Assignee: Intel Corporation
    Inventors: Ramesh Subashchandrabose, Anupam Mohanty, Rajat Agarwal
  • Mechanism to generate logically dedicated read and write channels in a memory controller
    Patent number: 7644248
    Abstract: According to one embodiment, a system is disclosed. The system includes a memory controller to schedule read commands to frames via a first dedicated command slot and to schedule write commands and corresponding data to frames via a dedicated second or third command slot.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: January 5, 2010
    Assignee: Intel Corporation
    Inventors: Ramesh Subashchandrabose, Anupam Mohanty, Rajat Agarwal
  • Commands scheduled for frequency mismatch bubbles
    Publication number: 20080159335
    Abstract: In some embodiments, a chip includes chip interface transmitters, a chip, and clock gearing logic. The transmitters are to transmit signals in frames including slots. The scheduler is to schedule signals at a first frequency including commands for first slots of the frames in general and commands for second slots of at least some frames immediately preceding frequency mismatch bubbles occurring when the frames are at a second frequency. The clock gearing logic is to provide the signals having the first frequency from the scheduler to the transmitters at the second frequency. Other embodiments are described.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 3, 2008
    Inventors: Ramesh Subashchandrabose, Anupam Mohanty, Rajat Agarwal
  • Mechanism to generate logically dedicated read and write channels in a memory controller
    Publication number: 20080077761
    Abstract: According to one embodiment, a system is disclosed. The system includes a memory controller to schedule read commands to frames via a first dedicated command slot and to schedule write commands and corresponding data to frames via a dedicated second or third command slot.
    Type: Application
    Filed: September 27, 2006
    Publication date: March 27, 2008
    Inventors: Ramesh Subashchandrabose, Anupam Mohanty, Rajat Agarwal