Abstract: Embodiments disclosed herein include transistor devices and methods of forming such transistor devices. In an embodiment a transistor comprises a substrate, and a fin that extends up from the substrate. In an embodiment, the fin comprises a source region, a drain region, and a channel region between the source region and the drain region. In an embodiment, the transistor further comprises and a cavity in the fin, where the cavity is below the channel region. In an embodiment, the transistor further comprises a gate stack over the fin.

Abstract: Fin shaping, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has substantially vertical upper sidewalls and outwardly tapered lower sidewalls. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack, and a second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

Abstract: Techniques are provided herein to form semiconductor devices on a substrate with an alternative crystallographic surface orientation. The techniques are particularly useful with respect to gate-all-around and forksheet transistor configurations. A substrate having a (110) crystallographic surface orientation forms the basis for the growth of alternating types of semiconductor layers. Both n-channel and p-channel transistors may be fabricated using silicon nanoribbons formed from some of the alternating semiconductor layers. The crystallographic surface orientation of the Si nanoribbons will reflect the same crystallographic surface orientation of the substrate, which leads to a higher hole mobility across the Si nanoribbons of the p-channel devices and an overall improved CMOS device performance.

Abstract: Embodiments of the disclosure include integrated circuit structures having source or drain dopant diffusion blocking layers. In an example, an integrated circuit structure includes a fin including silicon. A gate structure is over a channel region of the fin, the gate structure having a first side opposite a second side. A first source or drain structure is at the first side of the gate structure. A second source or drain structure is at the second side of the gate structure. The first and second source or drain structures include a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is in contact with the channel region of the fin, and the second semiconductor layer is on the first semiconductor layer. The first semiconductor layer has a greater concentration of germanium than the second semiconductor layer, and the second semiconductor layer includes boron dopant impurity atoms.

Abstract: Epitaxial oxide plugs are described for imposing strain on a channel region of a proximate channel region of a transistor. The oxide plugs form epitaxial and coherent contact with one or more source and drain regions adjacent to the strained channel region. The epitaxial oxide plugs can be used to either impart strain to an otherwise unstrained channel region (e.g., for a semiconductor body that is unstrained relative to an underlying buffer layer), or to restore, maintain, or increase strain within a channel region of a previously strained semiconductor body. The epitaxial crystalline oxide plugs have a perovskite crystal structure in some embodiments.

Abstract: Fin smoothing, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure, the protruding fin portion having substantially vertical sidewalls. The semiconductor fin further includes a sub-fin portion within an opening in the isolation structure, the sub-fin portion having a different semiconductor material than the protruding fin portion. The sub-fin portion has a width greater than or less than a width of the protruding portion where the sub-fin portion meets the protruding portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region at a first side of the gate stack, and a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.

Abstract: Embodiments of the disclosure include integrated circuit structures having source or drain dopant diffusion blocking layers. In an example, an integrated circuit structure includes a fin including silicon. A gate structure is over a channel region of the fin, the gate structure having a first side opposite a second side. A first source or drain structure is at the first side of the gate structure. A second source or drain structure is at the second side of the gate structure. The first and second source or drain structures include a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is in contact with the channel region of the fin, and the second semiconductor layer is on the first semiconductor layer. The first semiconductor layer has a greater concentration of germanium than the second semiconductor layer, and the second semiconductor layer includes boron dopant impurity atoms.

Abstract: An integrated circuit (IC) structure, an IC device, an IC device assembly, and a method of forming the same. The IC structure includes a transistor device comprising: a channel structure including a semiconductor material; a gate stack including a metal, the gate stack on the channel structure; a source structure in a first trench at a first side of the gate stack; a drain structure in a second trench at a second side of the gate stack; individual ones of the source structure and the drain structure including a source or drain (source/drain) liner comprising a doped epitaxial layer conformal with a surface of a corresponding one of the first trench and the second trench; a fill structure filling a portion of a corresponding one the first trench and the second trench, the fill structure adjacent to and compositionally different from the source/drain liner; and metal contact structures coupled to respective ones of the source structure and the drain structure.

Abstract: Fin smoothing, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure, the protruding fin portion having substantially vertical sidewalls. The semiconductor fin further includes a sub-fin portion within an opening in the isolation structure, the sub-fin portion having a different semiconductor material than the protruding fin portion. The sub-fin portion has a width greater than or less than a width of the protruding portion where the sub-fin portion meets the protruding portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region at a first side of the gate stack, and a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.

Abstract: Embodiments disclosed herein include transistor devices and methods of forming such transistor devices. In an embodiment a transistor comprises a substrate, and a fin that extends up from the substrate. In an embodiment, the fin comprises a source region, a drain region, and a channel region between the source region and the drain region. In an embodiment, the transistor further comprises and a cavity in the fin, where the cavity is below the channel region. In an embodiment, the transistor further comprises a gate stack over the fin.

Abstract: Fin shaping, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has substantially vertical upper sidewalls and outwardly tapered lower sidewalls. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack, and a second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

Abstract: Embodiments disclosed herein include transistor devices and methods of forming such transistor devices. In an embodiment a transistor comprises a substrate, and a fin that extends up from the substrate. In an embodiment, the fin comprises a source region, a drain region, and a channel region between the source region and the drain region. In an embodiment, the transistor further comprises and a cavity in the fin, where the cavity is below the channel region. In an embodiment, the transistor further comprises a gate stack over the fin.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having channel structures with sub-fin dopant diffusion blocking layers are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. The lower fin portion includes a dopant diffusion blocking layer on a first semiconductor layer doped to a first conductivity type. The upper fin portion includes a portion of a second semiconductor layer, the second semiconductor layer on the dopant diffusion blocking layer. An isolation structure is along sidewalls of the lower fin portion. A gate stack is over a top of and along sidewalls of the upper fin portion, the gate stack having a first side opposite a second side. A first source or drain structure at the first side of the gate stack.

Abstract: Gate-all-around integrated circuit structures having confined epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise germanium and boron, and a protective layer comprising germanium, silicon and boron that at least partially covers the epitaxial source or drain structures to provide low contact resistivity.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having channel structures with sub-fin dopant diffusion blocking layers are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. The lower fin portion includes a dopant diffusion blocking layer on a first semiconductor layer doped to a first conductivity type. The upper fin portion includes a portion of a second semiconductor layer, the second semiconductor layer on the dopant diffusion blocking layer. An isolation structure is along sidewalls of the lower fin portion. A gate stack is over a top of and along sidewalls of the upper fin portion, the gate stack having a first side opposite a second side. A first source or drain structure at the first side of the gate stack.

Abstract: Multiple strain states in epitaxial transistor channel material may be achieved through the incorporation of stress-relief defects within a seed material. Selective application of strain may improve channel mobility of one carrier type without hindering channel mobility of the other carrier type. A transistor structure may have a heteroepitaxial fin including a first layer of crystalline material directly on a second layer of crystalline material. Within the second layer, a number of defected regions of a threshold minimum dimension are present, which induces the first layer of crystalline material to relax into a lower-strain state. The defected regions may be introduced selectively, for example a through a masked impurity implantation, so that the defected regions may be absent in some transistor structures where a higher-strain state in the first layer of crystalline material is desired.

Abstract: Integrated circuit structures having asymmetric source and drain structures, and methods of fabricating integrated circuit structures having asymmetric source and drain structures, are described. For example, an integrated circuit structure includes a fin, and a gate stack over the fin. A first epitaxial source or drain structure is in a first trench in the fin at a first side of the gate stack. A second epitaxial source or drain structure is in a second trench in the fin at a second side of the gate stack, the second epitaxial source or drain structure deeper into the fin than the first epitaxial source or drain structure.

Abstract: Techniques are disclosed for forming integrated circuits configured with self-aligned isolation walls and alternate channel materials. The alternate channel materials in such integrated circuits provide improved carrier mobility through the channel. In an embodiment, an isolation wall is between sets of fins, at least some of the fins including an alternate channel material. In such cases, the isolation wall laterally separates the sets of fins, and the alternate channel material provides improved carrier mobility. For instance, in the case of an NMOS device the alternate channel material is a material optimized for electron flow, and in the case of a PMOS device the alternate channel material is a material optimized for hole flow.

Abstract: Integrated circuit structures including a buried etch-stop layer to help control transistor source/drain depth are provided herein. The buried etch-stop layer addresses the issue of the source/drain etch (or epi-undercut (EUC) etch) going below the bottom of the active height of the channel region, as such an issue can result in un-controlled sub-fin leakage that causes power consumption degradation and other undesired performance issues. The buried etch-stop layer is formed below the channel material, such as in the epitaxial stack that includes the channel material, and acts to slow the removal of material after the channel material has been removed when etching to form the source/drain trenches. In other words, the buried etch-stop layer includes different material from the channel material that can be etched, for at least one given etchant, at a relatively slower rate than the channel material to help control the source/drain trench depth.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having source or drain structures with a contact etch stop layer are described. In an example, an integrated circuit structure includes a fin including a semiconductor material, the fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first epitaxial source or drain structure is embedded in the fin at the first side of the gate stack. A second epitaxial source or drain structure is embedded in the fin at the second side of the gate stack, the first and second epitaxial source or drain structures including a lower semiconductor layer, an intermediate semiconductor layer and an upper semiconductor layer.