Patents by Inventor Anupama Thaploo

Anupama Thaploo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11489526
    Abstract: Described is a level-shifter that can save area between voltage domains with limited voltage differential, and further save power by steering current between two power supply rails. The level-shifter comprises: an input to receive a first signal between a first reference rail and a second reference rail; an output to provide a second signal the first reference rail and a third reference rail, wherein in a voltage level of the third reference rail is higher than a voltage level of the second reference rail, and wherein a voltage level of the first reference is lower than the voltage level of the second reference rail and the third reference rail; and a circuitry coupled to the input and the output, wherein the circuitry is to steer current from the third reference rail to the second reference rail.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: November 1, 2022
    Assignee: Intel Corporation
    Inventors: Andres Malavasi Mora, Jaydeep Kulkarni, Anupama Thaploo, Muhammad Khellah
  • Publication number: 20200358443
    Abstract: Described is a level-shifter that can save area between voltage domains with limited voltage differential, and further save power by steering current between two power supply rails. The level-shifter comprises: an input to receive a first signal between a first reference rail and a second reference rail; an output to provide a second signal the first reference rail and a third reference rail, wherein in a voltage level of the third reference rail is higher than a voltage level of the second reference rail, and wherein a voltage level of the first reference is lower than the voltage level of the second reference rail and the third reference rail; and a circuitry coupled to the input and the output, wherein the circuitry is to steer current from the third reference rail to the second reference rail.
    Type: Application
    Filed: May 22, 2020
    Publication date: November 12, 2020
    Applicant: Intel Corporation
    Inventors: Andres Malavasi Mora, Jaydeep Kulkarni, Anupama Thaploo, Muhammad Khellah
  • Patent number: 10666259
    Abstract: Described is a level-shifter that can save area between voltage domains with limited voltage differential, and further save power by steering current between two power supply rails. The level-shifter comprises: an input to receive a first signal between a first reference rail and a second reference rail; an output to provide a second signal the first reference rail and a third reference rail, wherein in a voltage level of the third reference rail is higher than a voltage level of the second reference rail, and wherein a voltage level of the first reference is lower than the voltage level of the second reference rail and the third reference rail; and a circuitry coupled to the input and the output, wherein the circuitry is to steer current from the third reference rail to the second reference rail.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Andres Malavasi Mora, Jaydeep Kulkarni, Anupama Thaploo, Muhammad Khellah
  • Patent number: 9685208
    Abstract: Embodiments include apparatuses, methods, and systems related to an assist circuit that may be coupled to one or more components of a memory system to selectively lower a supply voltage that is delivered to the component. For example, the assist circuit may be coupled to a plurality of bitcells (e.g., register file bitcells). The assist circuit may selectively lower the supply voltage delivered to the bitcells during at least a portion of a write operation and/or during an inactive state of the bitcells. Additionally, or alternatively, the assist circuit may be coupled to a read circuit to selectively lower the supply voltage delivered to the read circuit during an inactive state of the read circuit. The assist circuit may include a control transistor coupled in parallel with one or more diodes between a main supply rail and a supply node of the bitcells and/or read circuit.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: June 20, 2017
    Assignee: Intel Corporation
    Inventors: Jaydeep P. Kulkarni, Anupama Thaploo, Iqbal Rajwani, Kyung-Hoae Koo, Eric A. Karl, Muhammad Khellah
  • Publication number: 20160225419
    Abstract: Embodiments include apparatuses, methods, and systems related to an assist circuit that may be coupled to one or more components of a memory system to selectively lower a supply voltage that is delivered to the component. For example, the assist circuit may be coupled to a plurality of bitcells (e.g., register file bitcells). The assist circuit may selectively lower the supply voltage delivered to the bitcells during at least a portion of a write operation and/or during an inactive state of the bitcells. Additionally, or alternatively, the assist circuit may be coupled to a read circuit to selectively lower the supply voltage delivered to the read circuit during an inactive state of the read circuit. The assist circuit may include a control transistor coupled in parallel with one or more diodes between a main supply rail and a supply node of the bitcells and/or read circuit.
    Type: Application
    Filed: April 8, 2016
    Publication date: August 4, 2016
    Inventors: Jaydeep P. Kulkarni, Anupama Thaploo, Iqbal Rajwani, Kyung-Hoae Koo, Eric A. Karl, Muhammad Khellah
  • Patent number: 9355694
    Abstract: Embodiments include apparatuses, methods, and systems related to an assist circuit that may be coupled to one or more components of a memory system to selectively lower a supply voltage that is delivered to the component. For example, the assist circuit may be coupled to a plurality of bitcells (e.g., register file bitcells). The assist circuit may selectively lower the supply voltage delivered to the bitcells during at least a portion of a write operation and/or during an inactive state of the bitcells. Additionally, or alternatively, the assist circuit may be coupled to a read circuit to selectively lower the supply voltage delivered to the read circuit during an inactive state of the read circuit. The assist circuit may include a control transistor coupled in parallel with one or more diodes between a main supply rail and a supply node of the bitcells and/or read circuit.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: May 31, 2016
    Assignee: Intel Corporation
    Inventors: Jaydeep P. Kulkarni, Anupama Thaploo, Iqbal Rajwani, Kyung-Hoae Koo, Eric A. Karl, Muhammad Khellah
  • Publication number: 20150279438
    Abstract: Embodiments include apparatuses, methods, and systems related to an assist circuit that may be coupled to one or more components of a memory system to selectively lower a supply voltage that is delivered to the component. For example, the assist circuit may be coupled to a plurality of bitcells (e.g., register file bitcells). The assist circuit may selectively lower the supply voltage delivered to the bitcells during at least a portion of a write operation and/or during an inactive state of the bitcells. Additionally, or alternatively, the assist circuit may be coupled to a read circuit to selectively lower the supply voltage delivered to the read circuit during an inactive state of the read circuit. The assist circuit may include a control transistor coupled in parallel with one or more diodes between a main supply rail and a supply node of the bitcells and/or read circuit.
    Type: Application
    Filed: March 28, 2014
    Publication date: October 1, 2015
    Inventors: Jaydeep P. Kulkarni, Anupama Thaploo, Iqbal Rajwani, Kyung-Hoae Koo, Eric A. Karl, Muhammad Khellah