Patents by Inventor Anurag Chaudhry
Anurag Chaudhry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11107908Abstract: Embodiments herein describe techniques for a semi-conductor device comprising a channel having a first semiconductor material; a source contact coupled to the channel, comprising a first Heusler alloy; and a drain contact coupled to the channel, comprising a second Heusler alloy. The first Heusler alloy is lattice-matched to the first semiconductor material within a first predetermined threshold. A first Schottky barrier between the channel and the source contact, and a second Schottky barrier between the channel and the drain contact are negative, or smaller than another predetermined threshold. The source contact and the drain contact can be applied to a strained silicon transistor, an III-V transistor, a tunnel field-effect transistor, a dichalcogenide (MX2) transistor, and a junctionless nanowire transistor.Type: GrantFiled: July 1, 2016Date of Patent: August 31, 2021Assignee: Intel CorporationInventors: Sasikanth Manipatruni, Anurag Chaudhry, Dmitri E. Nikonov, Jasmeet S. Chawla, Christopher J. Wiegand, Kanwaljit Singh, Uygar E. Avci, Ian A. Young
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Patent number: 11056593Abstract: Techniques are disclosed for forming semiconductor integrated circuits including one or more of source and drain contacts and gate electrodes comprising crystalline alloys including a transition metal. The crystalline alloys help to reduce contact resistance to the semiconductor devices. In some embodiments of the present disclosure, this reduction in contact resistance is accomplished by aligning the work function of the crystalline alloy with the work function of the source and drain regions such that a Schottky barrier height associated with an interface between the crystalline alloys and the source and drain regions is in a range of 0.3 eV or less.Type: GrantFiled: September 12, 2017Date of Patent: July 6, 2021Assignee: Intel CorporationInventors: Sasikanth Manipatruni, Dmitri E. Nikonov, Uygar E. Avci, Christopher J. Wiegand, Anurag Chaudhry, Jasmeet S. Chawla, Ian A Young
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Publication number: 20210143819Abstract: Described is an apparatus which comprises: a 4-state input magnet; a first spin channel region adjacent to the 4-state input magnet; a 4-state output magnet; a second spin channel region adjacent to the 4-state input and output magnets; and a third spin channel region adjacent to the 4-state output magnet. Described in an apparatus which comprises: a 4-state input magnet; a first filter layer adjacent to the 4-state input magnet; a first spin channel region adjacent to the first filter layer; a 4-state output magnet; a second filter layer adjacent to the 4-state output magnet; a second spin channel region adjacent to the first and second filter layers; and a third spin channel region adjacent to the second filter layer.Type: ApplicationFiled: January 19, 2021Publication date: May 13, 2021Applicant: Intel CorporationInventors: Sasikanth Manipatruni, Ian A. Young, Dmitri E. Nikonov, Uygar E. Avci, Patrick Morrow, Anurag Chaudhry
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Patent number: 10944399Abstract: Described is an apparatus which comprises: a 4-state input magnet; a first spin channel region adjacent to the 4-state input magnet; a 4-state output magnet; a second spin channel region adjacent to the 4-state input and output magnets; and a third spin channel region adjacent to the 4-state output magnet. Described in an apparatus which comprises: a 4-state input magnet; a first filter layer adjacent to the 4-state input magnet; a first spin channel region adjacent to the first filter layer; a 4-state output magnet; a second filter layer adjacent to the 4-state output magnet; a second spin channel region adjacent to the first and second filter layers; and a third spin channel region adjacent to the second filter layer.Type: GrantFiled: December 23, 2016Date of Patent: March 9, 2021Assignee: Intel CorporationInventors: Sasikanth Manipatruni, Ian A. Young, Dmitri E. Nikonov, Uygar E. Avci, Patrick Morrow, Anurag Chaudhry
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Patent number: 10679782Abstract: Described is an apparatus which comprises: an input ferromagnet to receive a first charge current and to produce a first spin current; a first layer configured to convert the first spin current to a second charge current via spin orbit coupling (SOC), wherein at least a part of the first layer is coupled to the input ferromagnet; and a second layer configured to convert the second charge current to a second spin current via spin orbit coupling (SOC).Type: GrantFiled: September 9, 2015Date of Patent: June 9, 2020Assignee: Intel CorporationInventors: Sasikanth Manipatruni, Dmitri E. Nikonov, Anurag Chaudhry, Ian A. Young
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Publication number: 20200152781Abstract: Techniques are disclosed for forming semiconductor integrated circuits including one or more of source and drain contacts and gate electrodes comprising crystalline alloys including a transition metal. The crystalline alloys help to reduce contact resistance to the semiconductor devices. In some embodiments of the present disclosure, this reduction in contact resistance is accomplished by aligning the work function of the crystalline alloy with the work function of the source and drain regions such that a Schottky barrier height associated with an interface between the crystalline alloys and the source and drain regions is in a range of 0.3 eV or less.Type: ApplicationFiled: September 12, 2017Publication date: May 14, 2020Applicant: INTEL CORPORATIONInventors: Sasikanth Manipatruni, Dmitri E. Nikonov, Uygar E. Avci, Christopher J. Wiegand, Anurag Chaudhry, Jasmeet S. Chawla, Ian A. Young
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Patent number: 10622132Abstract: Described is an apparatus which comprises: an input magnet formed of one or more materials with a sufficiently high anisotropy and sufficiently low magnetic saturation to increase injection of spin currents; and a first interface layer coupled to the input magnet, wherein the first interface layer is formed of non-magnetic material such that the first interface layer and the input magnet together have sufficiently matched atomistic crystalline layers.Type: GrantFiled: June 24, 2015Date of Patent: April 14, 2020Assignee: Intel CorporationInventors: Sasikanth Manipatruni, Anurag Chaudhry, Dmitri E. Nikonov, David J. Michalak, Ian A. Young
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Patent number: 10608167Abstract: Described is an apparatus which comprises: a first non-magnetic conductor; a first spin orbit coupling (SOC) layer coupled to the first non-magnetic conductor; a first ferromagnet (FM) coupled to the SOC layer; a second FM; and an insulating FM sandwiched between the first and second FMs.Type: GrantFiled: September 10, 2015Date of Patent: March 31, 2020Assignee: Intel CorporationInventors: Dmitri E. Nikonov, Sasikanth Manipatruni, Anurag Chaudhry, Ian A. Young
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Publication number: 20190386661Abstract: Described is an apparatus which comprises: a 4-state input magnet; a first spin channel region adjacent to the 4-state input magnet; a 4-state output magnet; a second spin channel region adjacent to the 4-state input and output magnets; and a third spin channel region adjacent to the 4-state output magnet. Described in an apparatus which comprises: a 4-state input magnet; a first filter layer adjacent to the 4-state input magnet; a first spin channel region adjacent to the first filter layer; a 4-state output magnet; a second filter layer adjacent to the 4-state output magnet; a second spin channel region adjacent to the first and second filter layers; and a third spin channel region adjacent to the second filter layer.Type: ApplicationFiled: December 23, 2016Publication date: December 19, 2019Applicant: Intel CorporationInventors: Sasikanth Manipatruni, Ian A. Young, Dmitri E. Nikonov, Uygar E. Avci, Patrick Morrow, Anurag Chaudhry
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Patent number: 10483026Abstract: Described is an apparatus which comprises: an input ferromagnet to receive a first charge current and to produce a corresponding spin current; and a stack of metal layers configured to convert the corresponding spin current to a second charge current, wherein the stack of metal layers is coupled to the input magnet.Type: GrantFiled: June 24, 2015Date of Patent: November 19, 2019Assignee: Intel CorporationInventors: Sasikanth Manipatruni, Anurag Chaudhry, Dmitri E. Nikonov, Ian A. Young
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Patent number: 10387838Abstract: A system, a machine-readable storage medium storing instructions, and a computer-implemented method are described herein are directed to a Course Ingestion Engine (hereinafter “C.I. Engine”) that extracts a least a portion of a word present in a course description of an online course. The C.I. Engine determines, based on the at least one extracted portion of the word, at least one skill defined in a social networking service that can be acquired from content of the online course. The C.I. Engine recommends the online course to a target member account of the social networking service.Type: GrantFiled: April 28, 2016Date of Patent: August 20, 2019Assignee: Microsoft Technology Licensing, LLCInventors: Kevin Matthew Bevis, Sachin Rajendra, Anurag Chaudhry, Songzhe Cheng, Anirban Mitra, Kathy Hwang
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Publication number: 20190181249Abstract: Embodiments herein describe techniques for a semi-conductor device comprising a channel having a first semiconductor material; a source contact coupled to the channel, comprising a first Heusler alloy; and a drain contact coupled to the channel, comprising a second Heusler alloy. The first Heusler alloy is lattice-matched to the first semiconductor material within a first predetermined threshold. A first Schottky barrier between the channel and the source contact, and a second Schottky barrier between the channel and the drain contact are negative, or smaller than another predetermined threshold. The source contact and the drain contact can be applied to a strained silicon transistor, an III-V transistor, a tunnel field-effect transistor, a dichalcogenide (MX2) transistor, and a junctionless nanowire transistor.Type: ApplicationFiled: July 1, 2016Publication date: June 13, 2019Inventors: SASIKANTH MANIPATRUNI, ANURAG CHAUDHRY, DMITRI E. NIKONOV, JASMEET S. CHAWLA, CHRISTOPHER J. WIEGAND, KANWALJIT SINGH, UYGAR E. AVCI, IAN A. YOUNG
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Publication number: 20180327887Abstract: Refractory metal alloy targets for reducing particles in physical vapor deposition processing and refractory metal-based layer for integrated circuit applications (for example, crystallization barrier layers in non-volatile memory devices) are disclosed herein. An exemplary method for reducing particles in a PVD chamber include positioning a refractory metal alloy target in the PVD chamber, positioning a substrate in the PVD chamber a distance from the refractory metal alloy target, and sputtering material from the refractory metal alloy target to form a refractory metal-based layer over the substrate. The refractory metal alloy target includes a refractory metal (for example, tungsten or molybdenum) alloyed with a body-centered cubic (BCC) metal (for example, niobium, tantalum, vanadium, or a combination thereof). The BCC metal has a Young's modulus lower than a Young's modulus of the refractory metal.Type: ApplicationFiled: December 18, 2015Publication date: November 15, 2018Applicant: Intel CorporationInventors: Christopher J. WIEGAND, Philip YASHAR, Anurag CHAUDHRY
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Publication number: 20180240583Abstract: Described is an apparatus which comprises: an input ferromagnet to receive a first charge current and to produce a first spin current; a first layer configured to convert the first spin current to a second charge current via spin orbit coupling (SOC), wherein at least a part of the first layer is coupled to the input ferromagnet; and a second layer configured to convert the second charge current to a second spin current via spin orbit coupling (SOC).Type: ApplicationFiled: September 9, 2015Publication date: August 23, 2018Applicant: Intel CorporationInventors: Sasikanth Manipatruni, Dmitri E. Nikonov, Anurag Chaudhry, Ian A. Young
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Publication number: 20180240964Abstract: Described is an apparatus which comprises: a first non-magnetic conductor; a first spin orbit coupling (SOC) layer coupled to the first non-magnetic conductor; a first ferromagnet (FM) coupled to the SOC layer; a second FM; and an insulating FM sandwiched between the first and second FMs.Type: ApplicationFiled: September 10, 2015Publication date: August 23, 2018Applicant: Intel CorporationInventors: Dmitri E. Nikonov, Sasikanth Manipatruni, Anurag Chaudhry, Ian A. Young
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Publication number: 20180158587Abstract: Described is an apparatus which comprises: an input magnet formed of one or more materials with a sufficiently high anisotropy and sufficiently low magnetic saturation to increase injection of spin currents; and a first interface layer coupled to the input magnet, wherein the first interface layer is formed of non-magnetic material such that the first interface layer and the input magnet together have sufficiently matched atomistic crystalline layers.Type: ApplicationFiled: June 24, 2015Publication date: June 7, 2018Inventors: Sasikanth MANIPATRUNI, Anurag CHAUDHRY, Dmitri E. NIKONOV, David J. MICHALAK, Ian A. YOUNG
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Publication number: 20180158588Abstract: Described is an apparatus which comprises: an input ferromagnet to receive a first charge current and to produce a corresponding spin current; and a stack of metal layers configured to convert the corresponding spin current to a second charge current, wherein the stack of metal layers is coupled to the input magnet.Type: ApplicationFiled: June 24, 2015Publication date: June 7, 2018Inventors: Sasikanth MANIPATRUNI, Anurag CHAUDHRY, Dmitri E. NIKONOV, Ian A. YOUNG
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Patent number: 9947805Abstract: Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.Type: GrantFiled: May 10, 2016Date of Patent: April 17, 2018Assignee: Intel CorporationInventors: Chytra Pawashe, Kevin Lin, Anurag Chaudhry, Raseong Kim, Seiyon Kim, Kelin Kuhn, Sasikanth Manipatruni, Rafael Rios, Ian A. Young
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Patent number: 9911835Abstract: Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.Type: GrantFiled: January 19, 2017Date of Patent: March 6, 2018Assignee: Intel CorporationInventors: Roza Kotlyar, Stephen M. Cea, Gilbert Dewey, Benjamin Chu-Kung, Uygar E. Avci, Rafael Rios, Anurag Chaudhry, Thomas D. Linton, Jr., Ian A. Young, Kelin J. Kuhn
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Publication number: 20170318073Abstract: A system, a machine-readable storage medium storing instructions, and a computer-implemented method are described herein are directed to a Course Ingestion Engine (hereinafter “C.I. Engine”) that extracts a least a portion of a word present in a course description of an online course. The C.I. Engine determines, based on the at least one extracted portion of the word, at least one skill defined in a social networking service that can be acquired from content of the online course. The C.I. Engine recommends the online course to a target member account of the social networking service.Type: ApplicationFiled: April 28, 2016Publication date: November 2, 2017Inventors: Kevin Matthew Bevis, Sachin Rajendra, Anurag Chaudhry, Songzhe Cheng, Anirban Mitra, Kathy Hwang