Abstract: A smart data signals platform for artificial intelligence/machine learning (AI/ML)-based modeling and simulation is structured to pre-process input data by structuring previously unstructured data that relates to a structured data item and linking the structured data to the data item to generate a validated enriched dataset. The validated enriched dataset is used to generate a trigger signal by evaluating at least an aspect to the enriched dataset against at least one criterion that corresponds to a loss hypothesis. The trigger signal is used to automatically monitor subsequently received structured data, access corresponding unstructured data and generate an analysis dataset for one or more machine learning models. The one or more machine learning models generate a computer-based prediction based on the analysis dataset. The prediction can include a resource degradation indicator.

Abstract: A smart data signals platform for artificial intelligence/machine learning (AI/ML)-based modeling and simulation is structured to pre-process input data by structuring previously unstructured data that relates to a structured data item and linking the structured data to the data item to generate a validated enriched dataset. The validated enriched dataset is used to generate a trigger signal by evaluating at least an aspect to the enriched dataset against at least one criterion that corresponds to a loss hypothesis. The trigger signal is used to automatically monitor subsequently received structured data, access corresponding unstructured data and generate an analysis dataset for one or more machine learning models. The one or more machine learning models generate a computer-based prediction based on the analysis dataset. The prediction can include a resource degradation indicator.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with slotted active regions and methods of manufacture. The method includes: forming a mandrel on top of a diffusion region comprising a diffusion material; forming a first material over the mandrel and the diffusion region; removing the mandrel to form multiple spacers each having a thickness; depositing a second material over the spacers and the diffusion material; and forming slots in the diffusion region by removing a portion of the second material over the diffusion region and the underlying diffusion material.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with slotted active regions and methods of manufacture. The method includes: forming a mandrel on top of a diffusion region comprising a diffusion material; forming a first material over the mandrel and the diffusion region; removing the mandrel to form multiple spacers each having a thickness; depositing a second material over the spacers and the diffusion material; and forming slots in the diffusion region by removing a portion of the second material over the diffusion region and the underlying diffusion material.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with slotted active regions and methods of manufacture. The method includes: forming a mandrel on top of a diffusion region comprising a diffusion material; forming a first material over the mandrel and the diffusion region; removing the mandrel to form multiple spacers each having a thickness; depositing a second material over the spacers and the diffusion material; and forming slots in the diffusion region by removing a portion of the second material over the diffusion region and the underlying diffusion material.

Abstract: A method of forming contacts includes forming a plurality of transistor devices separated by shallow trench insulator regions, the transistor devices each comprising a semiconductor substrate, a buried insulator layer on the semiconductor bulk substrate, a semiconductor layer on the buried insulator layer, a high-k metal gate stack on the semiconductor layer and a gate electrode above the high-k metal gate stack, raised source/drain regions on the semiconductor layer, and a silicide contact layer above the raised source/drain regions and the gate electrode, providing an interlayer dielectric stack on the silicide contact layer and planarizing the interlayer dielectric stack, patterning a plurality of contacts through the interlayer dielectric stack onto the raised source/drain regions, and, for at least some of the contacts, patterning laterally extended contact regions above the contacts, the laterally extended contact regions extending over shallow trench insulator regions neighboring the corresponding rais

Abstract: A method of forming contacts includes forming a plurality of transistor devices separated by shallow trench insulator regions, the transistor devices each comprising a semiconductor substrate, a buried insulator layer on the semiconductor bulk substrate, a semiconductor layer on the buried insulator layer, a high-k metal gate stack on the semiconductor layer and a gate electrode above the high-k metal gate stack, raised source/drain regions on the semiconductor layer, and a silicide contact layer above the raised source/drain regions and the gate electrode, providing an interlayer dielectric stack on the silicide contact layer and planarizing the interlayer dielectric stack, patterning a plurality of contacts through the interlayer dielectric stack onto the raised source/drain regions, and, for at least some of the contacts, patterning laterally extended contact regions above the contacts, the laterally extended contact regions extending over shallow trench insulator regions neighboring the corresponding rais

Abstract: An electrical connection is provided between a source/drain of a planar transistor and a local interconnect or first metallization layer power rail, includes a first contact area electrically coupled to the source/drain, a second contact area electrically coupled to the first contact area and a gate of the transistor, and a V0 electrically coupled to the local interconnect or first metallization layer power rail. Trench silicide is absent from the transistor. A contact area-based power rail spine is also provided including a first contact area, a second contact area and adjacent V0 bi-directional staple both over and electrically coupled to the first contact area, and a V0 over and electrically coupled to the second contact area and the V0 bi-directional staple.

Abstract: At least one method, apparatus and system disclosed involves an antenna diode design for a semiconductor device. A first common diode operatively coupled to a ground node and to a p-well layer serving as an isolated p-well that is formed over a deep n-well that is adjacent to an n-well in a semiconductor device is provided. A first antenna diode formed on the isolated p-well operatively coupled to the p-well layer and operatively coupled to a first signal line of the semiconductor device is provided for discharging accumulated charges on the first signal line. A second antenna diode formed on the isolated p-well operatively coupled to the p-well layer and operatively coupled to a second signal line of semiconductor device is provided for discharging accumulated charges on the second signal line.

Abstract: At least one method, apparatus and system disclosed involves providing a design for manufacturing a semiconductor device. A first functional cell having a first width is placed on a circuit layout. A determination is made as to whether at least one transistor of the first functional cell is to be forward biased or reversed biased. A second functional cell having a second width is placed adjacent to the first functional cell on the circuit layout for providing a first biasing well within the total width of the first and second functional cells in response to determining that the at least one transistor is to be forward biased or reversed biased.

Abstract: At least one method, apparatus and system disclosed involves an antenna diode design for a semiconductor device. A first common diode operatively coupled to a ground node and to a p-well layer serving as an isolated p-well that is formed over a deep n-well that is adjacent to an n-well in a semiconductor device is provided. A first antenna diode formed on the isolated p-well operatively coupled to the p-well layer and operatively coupled to a first signal line of the semiconductor device is provided for discharging accumulated charges on the first signal line. A second antenna diode formed on the isolated p-well operatively coupled to the p-well layer and operatively coupled to a second signal line of semiconductor device is provided for discharging accumulated charges on the second signal line.

Abstract: At least one method, apparatus and system disclosed involves providing a design for manufacturing a semiconductor device. A first functional cell having a first width is placed on a circuit layout. A determination is made as to whether at least one transistor of the first functional cell is to be forward biased or reversed biased. A second functional cell having a second width is placed adjacent to the first functional cell on the circuit layout for providing a first biasing well within the total width of the first and second functional cells in response to determining that the at least one transistor is to be forward biased or reversed biased.

Abstract: At least one method, apparatus and system disclosed involves providing a design for manufacturing a semiconductor device. An operation modeling of a semiconductor device circuit design is performed. At least one transistor is identified for providing at least one of a first voltage for forward biasing the transistor or a second voltage for reverse biasing the transistor. Selectively providing a delay for adjusting a timing associated with the transistor based upon identifying the at least one transistor for providing the at least one of a first voltage for forward biasing the transistor or a second voltage for reverse biasing.

Abstract: An electronic fuse includes a body, an anode coupled to the body, and a cathode coupled to the body. Each of the anode and the cathode includes a first line contacting the body. The first line is discontinuous along its length and includes a first portion and a second portion with a space therebetween. A second line is disposed above the first line and a plurality of vias couple the first and second lines. The first portion of the first line is coupled to a first subset of the plurality of vias and the second portion of the first line is coupled to a second subset of the vias.

Abstract: Semiconductor fuses with epitaxial fuse link regions and fabrication methods thereof are presented. The methods include: fabricating a semiconductor fuse including an anode region and a cathode region electrically linked by a fuse link region, and the fabricating including: forming, epitaxially, the fuse link region between the anode region and the cathode region, wherein the fuse link region facilitates the semiconductor fuse open circuiting from applying a programming current between the anode region and the cathode region thereof. The semiconductor fuses include: an anode region and a cathode region electrically linked by a fuse link region, wherein the fuse link region includes an epitaxial structure and facilitates the semiconductor fuse open circuiting from applying a programming current between the anode region and the cathode region, wherein the epitaxial structure is in at least partial crystallographic alignment with the anode region and the cathode region of the semiconductor fuse.

Abstract: Methods of fabricating an integrated circuit with a fin-based fuse, and the resulting integrated circuit with a fin-based fuse are provided. In the method, a fin is created from a layer of semiconductor material and has a first end and a second end. The method provides for forming a conductive path on the fin from its first end to its second end. The conductive path is electrically connected to a programming device that is capable of selectively directing a programming current through the conductive path to cause a structural change in the conductive path to increase resistance across the conductive path.

Abstract: Embodiments of the present invention provide an improved decoupling capacitor structure. A contact region is disposed over a source/drain region of the decoupling capacitor structure. Each contact region is formed as a plurality of segments, wherein an inter-segment gap separates a segment of the plurality of segments from an adjacent segment of the plurality of segments. Embodiments may include multiple contact regions between two gate regions. Arrays of decoupling capacitors may arranged as an alternating “checkerboard” pattern of P-well and N-well structures, and may be oriented at a diagonal angle to a metallization layer to facilitate connections of multiple decoupling capacitors within the array.

Abstract: Methods for a low voltage antifuse device and the resulting devices are disclosed. Embodiments may include forming a plurality of fins above a substrate, removing a portion of a fin, forming a fin tip, forming a first area of a gate oxide layer above at least the fin tip, forming a second area of the gate oxide layer above a remaining portion of the plurality of fins, wherein the first area is thinner than the second area, and forming a gate over at least the fin tip to form an antifuse one-time programmable device.

Abstract: An OTP anti-fuse memory array without additional selectors and a manufacturing method are provided. Embodiments include forming wells of a first polarity in a substrate, forming a bitline of the first polarity in each well, and forming plural metal gates across each bitline, wherein no source/drain regions are formed between the metal gates.

Abstract: A method includes designating a cell mismatch parameter of a memory cell including a plurality of transistors and an initial value of a transistor mismatch parameter for each of the plurality of transistors. A critical current sensitivity parameter is determined for each of the plurality of transistors based on the transistor mismatch parameters in a computing apparatus. The cell mismatch parameter is distributed across the plurality of transistors in the computing apparatus to update the individual transistor mismatch parameters for each of the plurality of transistors based on the critical current sensitivity parameters and the cell mismatch parameter. The memory cell is simulated based on the individual transistor mismatch parameters to generate a simulation result.