Patents by Inventor Anurag P. Gupta
Anurag P. Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11902827Abstract: A network device may receive packets and may calculate, during a time interval, an arrival rate and a departure rate, of the packets, at one of multiple virtual output queues. The network device may calculate a current oversubscription factor based on the arrival rate and the departure rate, and may calculate a target oversubscription factor based on an average of previous oversubscription factors associated with the multiple virtual output queues. The network device may determine whether a difference exists between the target oversubscription factor and the current oversubscription factor and may calculate, when the difference exists, a scale factor based on the current oversubscription factor and the target oversubscription factor. The network device may calculate new scheduling weights based on prior scheduling weights and the scale factor, and may process packets received by the multiple virtual output queues based on the new scheduling weights.Type: GrantFiled: December 13, 2022Date of Patent: February 13, 2024Assignee: Juniper Networks, Inc.Inventors: Craig R. Frink, Anurag P. Gupta, Harshad B. Agashe, Weidong Xu
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Patent number: 11784925Abstract: An apparatus for switching network traffic includes an ingress packet forwarding engine and an egress packet forwarding engine. The ingress packet forwarding engine is configured to determine, in response to receiving a network packet, an egress packet forwarding engine for outputting the network packet and enqueue the network packet in a virtual output queue. The egress packet forwarding engine is configured to output, in response to a first scheduling event and to the ingress packet forwarding engine, information indicating the network packet in the virtual output queue and that the network packet is to be enqueued at an output queue for an output port of the egress packet forwarding engine. The ingress packet forwarding engine is further configured to dequeue, in response to receiving the information, the network packet from the virtual output queue and enqueue the network packet to the output queue.Type: GrantFiled: December 22, 2021Date of Patent: October 10, 2023Assignee: Juniper Networks, Inc.Inventors: Craig R. Frink, Weidong Xu, Anurag P. Gupta, Harshad B Agashe
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Publication number: 20230110668Abstract: A network device may receive packets and may calculate, during a time interval, an arrival rate and a departure rate, of the packets, at one of multiple virtual output queues. The network device may calculate a current oversubscription factor based on the arrival rate and the departure rate, and may calculate a target oversubscription factor based on an average of previous oversubscription factors associated with the multiple virtual output queues. The network device may determine whether a difference exists between the target oversubscription factor and the current oversubscription factor and may calculate, when the difference exists, a scale factor based on the current oversubscription factor and the target oversubscription factor. The network device may calculate new scheduling weights based on prior scheduling weights and the scale factor, and may process packets received by the multiple virtual output queues based on the new scheduling weights.Type: ApplicationFiled: December 13, 2022Publication date: April 13, 2023Inventors: Craig R. FRINK, Anurag P. GUPTA, Harshad B. AGASHE, Weidong XU
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Patent number: 11558775Abstract: A network device may receive packets and may calculate, during a time interval, an arrival rate and a departure rate, of the packets, at one of multiple virtual output queues. The network device may calculate a current oversubscription factor based on the arrival rate and the departure rate, and may calculate a target oversubscription factor based on an average of previous oversubscription factors associated with the multiple virtual output queues. The network device may determine whether a difference exists between the target oversubscription factor and the current oversubscription factor and may calculate, when the difference exists, a scale factor based on the current oversubscription factor and the target oversubscription factor. The network device may calculate new scheduling weights based on prior scheduling weights and the scale factor, and may process packets received by the multiple virtual output queues based on the new scheduling weights.Type: GrantFiled: February 16, 2021Date of Patent: January 17, 2023Assignee: Juniper Networks, Inc.Inventors: Craig R. Frink, Anurag P. Gupta, Harshad B. Agashe, Weidong Xu
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Publication number: 20220264364Abstract: A network device may receive packets and may calculate, during a time interval, an arrival rate and a departure rate, of the packets, at one of multiple virtual output queues. The network device may calculate a current oversubscription factor based on the arrival rate and the departure rate, and may calculate a target oversubscription factor based on an average of previous oversubscription factors associated with the multiple virtual output queues. The network device may determine whether a difference exists between the target oversubscription factor and the current oversubscription factor and may calculate, when the difference exists, a scale factor based on the current oversubscription factor and the target oversubscription factor. The network device may calculate new scheduling weights based on prior scheduling weights and the scale factor, and may process packets received by the multiple virtual output queues based on the new scheduling weights.Type: ApplicationFiled: February 16, 2021Publication date: August 18, 2022Inventors: Craig R. FRINK, Anurag P. GUPTA, Harshad B. AGASHE
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Publication number: 20220124030Abstract: An apparatus for switching network traffic includes an ingress packet forwarding engine and an egress packet forwarding engine. The ingress packet forwarding engine is configured to determine, in response to receiving a network packet, an egress packet forwarding engine for outputting the network packet and enqueue the network packet in a virtual output queue. The egress packet forwarding engine is configured to output, in response to a first scheduling event and to the ingress packet forwarding engine, information indicating the network packet in the virtual output queue and that the network packet is to be enqueued at an output queue for an output port of the egress packet forwarding engine. The ingress packet forwarding engine is further configured to dequeue, in response to receiving the information, the network packet from the virtual output queue and enqueue the network packet to the output queue.Type: ApplicationFiled: December 22, 2021Publication date: April 21, 2022Inventors: Craig R. Frink, Weidong Xu, Anurag P. Gupta, Harshad B Agashe
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Patent number: 11240151Abstract: An apparatus for switching network traffic includes an ingress packet forwarding engine and an egress packet forwarding engine. The ingress packet forwarding engine is configured to determine, in response to receiving a network packet, an egress packet forwarding engine for outputting the network packet and enqueue the network packet in a virtual output queue. The egress packet forwarding engine is configured to output, in response to a first scheduling event and to the ingress packet forwarding engine, information indicating the network packet in the virtual output queue and that the network packet is to be enqueued at an output queue for an output port of the egress packet forwarding engine. The ingress packet forwarding engine is further configured to dequeue, in response to receiving the information, the network packet from the virtual output queue and enqueue the network packet to the output queue.Type: GrantFiled: December 10, 2019Date of Patent: February 1, 2022Assignee: Juniper Networks, Inc.Inventors: Craig R. Frink, Weidong Xu, Anurag P. Gupta, Harshad B Agashe
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Publication number: 20210176171Abstract: An apparatus for switching network traffic includes an ingress packet forwarding engine and an egress packet forwarding engine. The ingress packet forwarding engine is configured to determine, in response to receiving a network packet, an egress packet forwarding engine for outputting the network packet and enqueue the network packet in a virtual output queue. The egress packet forwarding engine is configured to output, in response to a first scheduling event and to the ingress packet forwarding engine, information indicating the network packet in the virtual output queue and that the network packet is to be enqueued at an output queue for an output port of the egress packet forwarding engine. The ingress packet forwarding engine is further configured to dequeue, in response to receiving the information, the network packet from the virtual output queue and enqueue the network packet to the output queue.Type: ApplicationFiled: December 10, 2019Publication date: June 10, 2021Inventors: Craig R. Frink, Weidong Xu, Anurag P. Gupta, Harshad B. Agashe
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Patent number: 9116814Abstract: A data read/write system includes a system clock, a single port memory, a cache memory that is separate from the single port memory, and a controller coupled to an instruction pipeline. The controller receives, via the instruction pipeline, first data to write to an address of the single port memory, and further receives, via the instruction pipeline, a request to read second data from the single port memory. The controller stores the first data in the cache memory, and retrieves the second data from either the cache memory or the single port memory during one or more first clock cycles of the system clock. The controller copies the first data from the cache memory and stores the first data at the address in the single port memory during a second clock cycle of the system clock that is different than the one or more first clock cycles.Type: GrantFiled: November 27, 2013Date of Patent: August 25, 2015Assignee: Juniper Networks, Inc.Inventors: Jianhui Huang, Sharada Yeluri, Jean-Marc Frailong, Jeffrey G. Libby, Anurag P. Gupta, Paul Coelho
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Patent number: 8954409Abstract: In general, techniques of the present disclosure relate to synchronizing concurrent access to multiple portions of a data structure. In one example, a method includes, sequentially selecting a plurality of requests from a request queue, wherein at least one of the requests specifies a plurality of requested synchronization objects for corresponding candidate portions of a data structure to which to apply an operation associated with a data element. The method also includes querying one or more sets of identifiers to determine whether one or more of the requested synchronizations objects specified by the selected request are acquirable. The method also includes acquiring each of the requested synchronization objects that are acquirable. The method includes, responsive to acquiring all of the one or more requested synchronization objects, selecting a subset of the candidate portions of the data structure and applying the operation only to the selected subset of the candidate portions.Type: GrantFiled: September 22, 2011Date of Patent: February 10, 2015Assignee: Juniper Networks, Inc.Inventors: Oren Kerem, Jeffrey G. Libby, Deepak Goel, David J. Ofelt, Anurag P. Gupta
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Patent number: 8924687Abstract: A data read/write system receives a key associated with a data read request. The data read/write system hashes the key to obtain a first hash value and hashes the key to obtain a second hash value, where the second hash value is different than the first hash value. The data read/write system obtains a pointer from a pointer array using the first and second hash values, and uses one or more bits of the pointer and the first hash value to retrieve data from a data look-up array.Type: GrantFiled: July 8, 2013Date of Patent: December 30, 2014Assignee: Juniper Networks, Inc.Inventors: Jean-Marc Frailong, Anurag P Gupta, David Talaski, Sanjeev Singh
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Patent number: 8843805Abstract: In general, techniques are described for efficiently and transparently partitioning a physical address space of a DRAM part lacking dedicated error protection circuitry to supply addressable error protection bytes for use in detecting and/or correcting bit errors elsewhere present in the physical address space. In one example, a network device includes a DRAM and a memory controller that receives a write command to write data to the DRAM. An address translation module of the memory controller logically partitions the DRAM to define a plurality of physically addressable sections that includes an error protection section for storing error protection bits and one or more data storage sections. The memory controller defines a contiguous logical address space representing the data storage sections. A DRAM controller of the network device communicates with the DRAM to store the data to one of the data storage sections in accordance with the contiguous logical address space.Type: GrantFiled: March 16, 2012Date of Patent: September 23, 2014Assignee: Juniper Networks, Inc.Inventors: Deepak Goel, Jeffrey G. Libby, Anurag P. Gupta, Abhijit Ghosh, David J. Ofelt
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Patent number: 8813015Abstract: A system includes a memory and a controller. The controller may include a group of pads and an allocation register. The controller is configured to receive input signals corresponding to the group and allocate each one of the pads to output one of the input signals based on a configuration of pins of the memory. The controller is also configured to redirect the input signals, within the controller, based on the allocation of the pads and output the input signals from the controller into the pads.Type: GrantFiled: December 21, 2012Date of Patent: August 19, 2014Assignee: Juniper Networks, Inc.Inventors: Srinivas Vaduvatha, Srinivas Venkataraman, Anurag P. Gupta, Praveen Garapally, Norman Bristol, Dibyendu Sen
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Patent number: 8799909Abstract: Systems and methods of various embodiments provide mechanisms to support synchronous and asynchronous transactions. Distinct encodings allow an instruction to choose whether to perform any operation synchronously or asynchronously. Separate synchronous and asynchronous result registers hold the data returned in the most recent replies received for synchronous and asynchronous transaction requests, respectively. A status bit indicates whether an asynchronous transaction request is currently outstanding.Type: GrantFiled: December 23, 2008Date of Patent: August 5, 2014Assignee: Juniper Networks, Inc.Inventors: Jeffrey G. Libby, Jean-Marc Frailong, Avanindra Godbole, Sharada Yeluri, Anurag P. Gupta, John Keen
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Patent number: 8706896Abstract: Output logic generates read requests using a programmable schedule that controls read bandwidth for multiple data streams and stores the read requests in a queuing device. The output logic also dequeues the read requests based on a similar programmable schedule, forwards the read requests to the memory, and reads data units from the memory based on the read requests.Type: GrantFiled: August 16, 2012Date of Patent: April 22, 2014Assignee: Juniper Networks, Inc.Inventors: Song Zhang, Phil Lacroute, Anurag P. Gupta, Raymond M. Lim, Avanindra Godbole, Debashis Basu
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Patent number: 8627007Abstract: A data read/write system includes a system clock, a single port memory, a cache memory that is separate from the single port memory, and a controller coupled to an instruction pipeline. The controller receives, via the instruction pipeline, first data to write to an address of the single port memory, and further receives, via the instruction pipeline, a request to read second data from the single port memory. The controller stores the first data in the cache memory, and retrieves the second data from either the cache memory or the single port memory during one or more first clock cycles of the system clock. The controller copies the first data from the cache memory and stores the first data at the address in the single port memory during a second clock cycle of the system clock that is different than the one or more first clock cycles.Type: GrantFiled: October 28, 2009Date of Patent: January 7, 2014Assignee: Juniper Networks, Inc.Inventors: Jianhui Huang, Sharada Yeluri, Jean-Marc Frailong, Jeffrey G. Libby, Anurag P. Gupta, Paul Coelho
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Patent number: 8520675Abstract: Methods and systems consistent with the present invention provide efficient packet replication in a router in order to multicast a stream of data. Packets are replicated and processed in a multithreaded environment. Embodiments consistent with the present invention implement a two-stage process for packet replication. The first stage thread will recirculate the packet to multiple second-stage threads. These second-stage threads will then create one or more outgoing copies of the packet. In this way, the copies are handled by multiple threads running in parallel.Type: GrantFiled: December 23, 2008Date of Patent: August 27, 2013Assignee: Juniper Networks, Inc.Inventors: Jean-Marc Frailong, Jeffrey G. Libby, Anurag P. Gupta, John Keen, Rajesh Nair, Avanindra Godbole, Sharada Yeluri
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Patent number: 8498306Abstract: Data units received by a network device may be classified into traffic flow classes in which the determined traffic flow class for a data unit may be dynamically refined as the data unit is processed by the network device. A dispatch component of the network device may receive data units associated with traffic flow classes. Parallel processing engines of the network device may receive the data units from the dispatch component and may generate, for a least one of the data units, a plurality of dynamically refined indications of the traffic flow class to which the data unit belongs. Additionally, an ordering component of the network device may include a plurality of re-order queues, where the at least one data unit successively progresses through at least two of the re-order queues in an order defined by the plurality of dynamically refined indications of the traffic flow class.Type: GrantFiled: March 10, 2011Date of Patent: July 30, 2013Assignee: Juniper Networks, Inc.Inventors: Jean-Marc Frailong, Sharada Yeluri, Anurag P Gupta, Jeffrey G Libby, Edwin Su
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Patent number: 8484439Abstract: A data read/write system receives a key associated with a data read request. The data read/write system hashes the key to obtain a first hash value and hashes the key to obtain a second hash value, where the second hash value is different than the first hash value. The data read/write system obtains a pointer from a pointer array using the first and second hash values, and uses one or more bits of the pointer and the first hash value to retrieve data from a data look-up array.Type: GrantFiled: October 27, 2009Date of Patent: July 9, 2013Assignee: Juniper Networks, Inc.Inventors: Jean-Marc Frailong, Anurag P. Gupta, David Talaski, Sanjeev Singh
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Patent number: 8462804Abstract: A system manages a buffer having a group of entries. The system receives information relating to a read request for a memory. The system determines whether an entry in the buffer contains valid information. If the entry is determined to contain valid information, the system transmits the information in the entry in an error message. The system may then store the received information in the entry. In another implementation, the system stores data in one of the entries of the buffer, removes an address corresponding to the one entry from an address list, and starts a timer associated with the one entry. The system also determines whether the timer has exceeded a predetermined value, transferring the data from the one entry when the timer has exceeded the predetermined value, and adds the address back to the address list.Type: GrantFiled: December 16, 2010Date of Patent: June 11, 2013Assignee: Juniper Networks, Inc.Inventors: Anurag P. Gupta, Song Zhang