Abstract: An integrated circuit (IC) includes input/output (I/O) ports, each operating using one of a pair of unequal power supplies during normal operation of the IC. A lower supply of the pair of unequal power supplies is required to be used as the power supply for the I/O port when a first input signal to the IC is received from an external source on a first I/O port of the I/O ports. The voltage range of the logic excursions of the first input signal is greater than the range from a magnitude of the lower supply to a constant reference potential. A regulation loop derives a derived lower supply having a magnitude equaling that of the lower supply from the higher supply of the pair of unequal power supplies, and applies the derived lower supply on a power supply node of the first I/O port.

Abstract: An integrated circuit (IC) includes input/output (I/O) ports, each operating using one of a pair of unequal power supplies during normal operation of the IC. A lower supply of the pair of unequal power supplies is required to be used as the power supply for the I/O port when a first input signal to the IC is received from an external source on a first I/O port of the I/O ports. The voltage range of the logic excursions of the first input signal is greater than the range from a magnitude of the lower supply to a constant reference potential. A regulation loop derives a derived lower supply having a magnitude equaling that of the lower supply from the higher supply of the pair of unequal power supplies, and applies the derived lower supply on a power supply node of the first I/O port.

Abstract: A multi-mode amplifier with configurable DC-coupled or AC-coupled output is described. In one design, the multi-mode amplifier includes an amplifier and at least one DC level shifting circuit. The amplifier receives and amplifies an input signal and provides an output signal that is suitable for DC coupling to a load in a DC-coupled mode and for AC coupling to the load in an AC-coupled mode. The at least one DC level shifting circuit performs DC level shifting for at least one (e.g., input and/or output) common-mode voltage of the amplifier and is controlled based on whether the amplifier is operating in the DC-coupled or AC-coupled mode. The amplifier operates between VDD and VNEG supplies in the DC-coupled mode and between VDD and VSS supplies in the AC-coupled mode. The amplifier may include at least one gain stage, an internal DC level shifting circuit, and an output stage.

Abstract: A multi-mode amplifier with configurable DC-coupled or AC-coupled output is described. In one design, the multi-mode amplifier includes an amplifier and at least one DC level shifting circuit. The amplifier receives and amplifies an input signal and provides an output signal that is suitable for DC coupling to a load in a DC-coupled mode and for AC coupling to the load in an AC-coupled mode. The at least one DC level shifting circuit performs DC level shifting for at least one (e.g., input and/or output) common-mode voltage of the amplifier and is controlled based on whether the amplifier is operating in the DC-coupled or AC-coupled mode. The amplifier operates between VDD and VNEG supplies in the DC-coupled mode and between VDD and VSS supplies in the AC-coupled mode. The amplifier may include at least one gain stage, an internal DC level shifting circuit, and an output stage.

Abstract: A system and method for converting an analog signal to a digital signal is provided. The analog to digital conversion is achieved without a dedicated sample-and-hold circuit. An ADC stage, preferably the front-end stage in the case of a pipeline ADC, samples the input voltage within a quantizer and within a residue generator. The sampling is performed with associated clocking signals and with switch capacitors also fulfilling the comparison with threshold voltages, within the quantizer and the generation of a residue signal within the residue generator.

Abstract: A system and method for converting an analog signal to a digital signal is provided. The analog to digital conversion is achieved without a dedicated sample-and-hold circuit. An ADC stage, preferably the front-end stage in the case of a pipeline ADC, samples the input voltage within a quantizer and within a residue generator. The sampling is performed with associated clocking signals and with switch capacitors also fulfilling the comparison with threshold voltages, within the quantizer and the generation of a residue signal within the residue generator.