Patents by Inventor Anurag Tomar

Anurag Tomar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for implementing pipeline flip-flops
    Patent number: 9262359
    Abstract: Disclosed is a method, system, and computer program product for automated implementation of pipeline flip-flops in an electronic design. Two operating modes can be used either together or separately to implement pipeline flip-flops. An analysis mode is employed to perform a determination of the number of stages of pipeline flip-flops needed for particular portions of an electronic design. A placement stage is used to place the pipeline flip-flops in the layout.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: February 16, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: David C. Noice, Anurag Tomar, Scot A. Woodward, Adrian Aloysius Hendroff, Dennis Huang
  • Flat placement of cells on non-integer multiple height rows in a digital integrated circuit layout
    Patent number: 7802219
    Abstract: The various embodiments of the present invention generally relate to systems, methods, and computer program products for placement of at least one cell in a digital integrated circuit layout. A global placement grid of coordinates is formed, where the coordinates represent horizontal and vertical directions. A local placement grid of coordinates is also formed for at least one local region, where the local placement grid of coordinates represent horizontal and vertical directions, and where the at least one local region is adapted to support non-integer multiple height rows. At least one cell is associated with the at least one local region formed, and the cell can be placed in the local placement grid of the local region.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: September 21, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Anurag Tomar, Dave Noice
  • FLAT PLACEMENT OF CELLS ON NON-INTEGER MULTIPLE HEIGHT ROWS IN A DIGITAL INTEGRATED CIRCUIT LAYOUT
    Publication number: 20080134118
    Abstract: The various embodiments of the present invention generally relate to systems, methods, and computer program products for placement of at least one cell in a digital integrated circuit layout. A global placement grid of coordinates is formed, where the coordinates represent horizontal and vertical directions. A local placement grid of coordinates is also formed for at least one local region, where the local placement grid of coordinates represent horizontal and vertical directions, and where the at least one local region is adapted to support non-integer multiple height rows. At least one cell is associated with the at least one local region formed, and the cell can be placed in the local placement grid of the local region.
    Type: Application
    Filed: November 30, 2006
    Publication date: June 5, 2008
    Applicant: Cadence Design Systems, Inc.
    Inventors: Anurag Tomar, Dave Noice