Patents by Inventor Anwar Mohammed

Anwar Mohammed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050017256
    Abstract: Light emitting device die having a mesa configuration on a substrate and an electrode on the mesa are attached to a submount in a flip-chip configuration by forming predefined pattern of conductive die attach material on at least one of the electrode and the submount and mounting the light emitting device die to the submount. The predefined pattern of conductive die attach material is selected so as to prevent the conductive die attach material from contacting regions of having opposite conductivity types when the light emitting device die is mounted to the submount. The predefined pattern of conductive die attach material may provide a volume of die attach material that is less than a volume defined by an area of the electrode and a distance between the electrode and the submount. Light emitting device dies having predefined patterns of conductive die attach material are also provided.
    Type: Application
    Filed: August 17, 2004
    Publication date: January 27, 2005
    Inventors: David Slater, Jayesh Bharathan, John Edmond, Mark Raffeto, Anwar Mohammed, Peter Andrews, Gerald Negley
  • Publication number: 20040200882
    Abstract: Bonding of flip-chip mounted light emitting devices having an irregular configuration is provided. Light emitting diodes having a shaped substrate are bonded to a submount by applying forces to the substrate an a manner such that shear forces within the substrate do not exceed a failure threshold of the substrate. Bonding a light emitting diode to a submount may be provided by applying force to a surface of a substrate of the light emitting diode that is oblique to a direction of motion of the light emitting diode to thermosonically bond the light emitting diode to the submount. Collets for use in bonding shaped substrates to a submount and systems for bonding shaped substrates to a submount are also provided.
    Type: Application
    Filed: April 27, 2004
    Publication date: October 14, 2004
    Inventors: David B. Slater, Jayesh Bharathan, John Edmond, Mark Raffetto, Anwar Mohammed, Peter S. Andrews, Gerald H. Negley
  • Patent number: 6747298
    Abstract: Bonding of flip-chip mounted light emitting devices having an irregular configuration is provided. Light emitting diodes having a shaped substrate are bonded to a submount by applying forces to the substrate an a manner such that shear forces within the substrate do not exceed a failure threshold of the substrate. Bonding a light emitting diode to a submount may be provided by applying force to a surface of a substrate of the light emitting diode that is oblique to a direction of motion of the light emitting diode to thermosonically bond the light emitting diode to the submount. Collets for use in bonding shaped substrates to a submount and systems for bonding shaped substrates to a submount are also provided.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: June 8, 2004
    Assignee: Cree, Inc.
    Inventors: David B. Slater, Jr., Jayesh Bharathan, John Edmond, Mark Raffetto, Anwar Mohammed, Peter S. Andrews, Gerald H. Negley
  • Patent number: 6681483
    Abstract: A printed circuit architecture includes a relatively thick, stiffening base of thermally and electrically conductive material, and a laminate of conductive layers including a printed circuit structure, interleaved with dielectric layers, disposed atop the base. The patterned conductive layers contain an integrated circuit structure that is configured to provide RF signaling, microstrip shielding, and digital and analog control signal leads, and DC power. Low inductance electrical connectivity among the conductive layers and also between conductive layers and the base is provided by a plurality of conductive bores. Selected bores are counter-drilled at the RF signaling layer and filled with insulating plugs, which prevent shorting of the RF signal trace layer to ground, during solder reflow connection of leads of circuit components to the RF signaling layer.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: January 27, 2004
    Assignee: Remec, Inc.
    Inventors: E. James Crescenzi, Jr., Anwar A. Mohammed
  • Publication number: 20030042507
    Abstract: Bonding of flip-chip mounted light emitting devices having an irregular configuration is provided. Light emitting diodes having a shaped substrate are bonded to a submount by applying forces to the substrate an a manner such that shear forces within the substrate do not exceed a failure threshold of the substrate. Bonding a light emitting diode to a submount may be provided by applying force to a surface of a substrate of the light emitting diode that is oblique to a direction of motion of the light emitting diode to thermosonically bond the light emitting diode to the submount. Collets for use in bonding shaped substrates to a submount and systems for bonding shaped substrates to a submount are also provided.
    Type: Application
    Filed: June 27, 2002
    Publication date: March 6, 2003
    Inventors: David B. Slater, Jayesh Bharathan, John Edmond, Mark Raffetto, Anwar Mohammed, Peter S. Andrews, Gerald H. Negley
  • Publication number: 20030045015
    Abstract: Light emitting device die having a mesa configuration on a substrate and an electrode on the mesa are attached to a submount in a flip-chip configuration by forming predefined pattern of conductive die attach material on at least one of the electrode and the submount and mounting the light emitting device die to the submount. The predefined pattern of conductive die attach material is selected so as to prevent the conductive die attach material from contacting regions of having opposite conductivity types when the light emitting device die is mounted to the submount. The predefined pattern of conductive die attach material may provide a volume of die attach material that is less than a volume defined by an area of the electrode and a distance between the electrode and the submount. Light emitting device dies having predefined patterns of conductive die attach material are also provided.
    Type: Application
    Filed: June 27, 2002
    Publication date: March 6, 2003
    Inventors: David B. Slater, Jayesh Bharathan, John Edmond, Mark Raffetto, Anwar Mohammed, Peter S. Andrews, Gerald H. Negley
  • Patent number: 6466113
    Abstract: A printed circuit architecture includes a relatively thick, stiffening base of thermally and electrically conductive material, and a laminate of conductive layers including a printed circuit structure, interleaved with dielectric layers, disposed atop the base. The patterned conductive layers contain an integrated circuit structure that is configured to provide RF signaling, microstrip shielding, and digital and analog control signal leads, and DC power. Low inductance electrical connectivity among the conductive layers and also between conductive layers and the base is provided by a plurality of conductive bores. Selected bores are counter-drilled at the RF signaling layer and filled with insulating plugs, which prevent shorting of the RF signal trace layer to ground, during solder reflow connection of leads of circuit components to the RF signaling layer.
    Type: Grant
    Filed: January 21, 2000
    Date of Patent: October 15, 2002
    Assignee: Spectrian Corporation
    Inventors: E. James Crescenzi, Jr., Anwar A. Mohammed
  • Publication number: 20020113673
    Abstract: A printed circuit architecture includes a relatively thick, stiffening base of thermally and electrically conductive material, and a laminate of conductive layers including a printed circuit structure, interleaved with dielectric layers, disposed atop the base. The patterned conductive layers contain an integrated circuit structure that is configured to provide RF signaling, microstrip shielding, and digital and analog control signal leads, and DC power. Low inductance electrical connectivity among the conductive layers and also between conductive layers and the base is provided by a plurality of conductive bores. Selected bores are counter-drilled at the RF signaling layer and filled with insulating plugs, which prevent shorting of the RF signal trace layer to ground, during solder reflow connection of leads of circuit components to the RF signaling layer.
    Type: Application
    Filed: April 18, 2002
    Publication date: August 22, 2002
    Applicant: SPECTRIAN CORPORATION
    Inventors: E. James Crescenzi, Anwar A. Mohammed
  • Patent number: 5371029
    Abstract: A process for forming a leadless chip resistor capacitor carrier by forming a first capacitor plate using a first thick film printing sequence and forming the second capacitor plate using a second thin film printing sequence.
    Type: Grant
    Filed: March 24, 1993
    Date of Patent: December 6, 1994
    Assignee: National Semiconductor Corporation
    Inventors: Azzam A. Abdo, Anwar A. Mohammed