Patents by Inventor Anxiao Jiang
Anxiao Jiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210125069Abstract: Computer-aided methods for performing computations using adversarially-robust neural networks is disclosed that includes providing a uncoded neural network comprising a plurality of neurons and associated inputs for each of the plurality of neurons, each neuron configured to perform a calculation according to an activation function. The method further includes transforming, using the computing device, at least one uncoded neuron into a coded neuron by adding, using the computing device, an error correcting code as an additional input to the at least one uncoded neuron, the error correcting code comprising a redundant combination of the associated inputs off the uncoded neuron, and revising, using the computing device, the activation function of the at least one uncoded neuron to accommodate the error correcting code as the additional input.Type: ApplicationFiled: October 29, 2020Publication date: April 29, 2021Applicants: Washington University, Texas A&M University, California Institute of TechnologyInventors: Netanel Raviv, Jehoshua Bruck, Siddharth Jain, Anxiao Jiang, Pulakesh Upadhyaya
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Patent number: 10379945Abstract: Techniques are disclosed for generating codes for representation of data in memory devices that may avoid the block erasure operation in changing data values. Data values comprising binary digits (bits) can be encoded and decoded using the generated codes, referred to as codewords, such that the codewords may comprise a block erasure-avoiding code, in which the binary digits of a data message m can be encoded such that the encoded data message can be stored into multiple memory cells of a data device and, once a memory cell value is changed from a first logic value to a second logic value, the value of the memory cell may remain at the second logic value, regardless of subsequently received messages, until a block erasure operation on the memory cell.Type: GrantFiled: January 14, 2015Date of Patent: August 13, 2019Assignees: CALIFORNIA INSTITUTE OF TECHNOLOGY, THE TEXAS A & M UNIVERSITY SYSTEMInventors: Eyal En Gad, Yue Li, Joerg Kliewer, Michael Langberg, Anxiao Jiang, Jehoshua Bruck
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Patent number: 9983808Abstract: The reliability of NAND flash memory decreases rapidly as density increases, preventing the wide adoptions of flash-based storage systems. A novel data representation scheme named rank modulation (RM) is discussed for improving NAND flash reliability. RM encodes data using the relative orders of memory cell voltages, which is inherently resilient to asymmetric errors. For studying the effectiveness of RM in flash, RM is adapted to make it simple to implement with existing flash memories. The implementation is evaluated under different types of noise of 20 nm flash memory. Results show that RM offers significantly lower cell error rates compared to the current data representation in flash at typical P/E cycles. RM is applied to flash-based archival storage and shows that RM brings up to six times longer data retention time for 16 nm flash memory.Type: GrantFiled: December 10, 2015Date of Patent: May 29, 2018Assignee: California Institute of TechnologyInventors: Yue Li, Eyal En Gad, Anxiao Jiang, Jehoshua Bruck
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Patent number: 9946475Abstract: Both rewriting and error correction are technologies usable for non-volatile memories, such as flash memories. A coding scheme is disclosed herein that combines rewriting and error correction for the write-once memory model. In some embodiments, code construction is based on polar codes, and supports any number of rewrites and corrects a substantial number of errors. The code may be analyzed for a binary symmetric channel. The results can be extended to multi-level cells and more general noise models.Type: GrantFiled: July 5, 2013Date of Patent: April 17, 2018Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGYInventors: Anxiao Jiang, Yue Li, Eyal En Gad, Michael Langberg, Jehoshua Bruck
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Patent number: 9916197Abstract: Rank modulation has been recently proposed as a scheme for storing information in flash memories. Three improved aspects are disclosed. In one aspect the minimum push-up scheme, for storing data in flash memories is provided. It aims at minimizing the cost of changing the state of the memory. In another aspect, multi-cells, used for storing data in flash memories is provided. Each transistor is replaced with a multi-cell of mm transistors connected in parallel. In yet another aspect, multi-permutations, are provided. The paradigm of representing information with permutations is generalized to the case where the number of cells in each level is a constant greater than one. In yet another aspect, rank-modulation rewriting schemes which take advantage of polar codes, are provided for use with flash memory.Type: GrantFiled: June 2, 2015Date of Patent: March 13, 2018Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGYInventors: Anxiao Jiang, Eyal En Gad, Jehoshua Bruck, Eitan Yaakobi
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Patent number: 9666280Abstract: Rank modulation has been recently proposed as a scheme for storing information in flash memories. Three improved aspects are disclosed. In one aspect the minimum push-up scheme, for storing data in flash memories is provided. It aims at minimizing the cost of changing the state of the memory. In another aspect, multi-cells, used for storing data in flash memories is provided. Each transistor is replaced with a multi-cell of m transistors connected in parallel. In yet another aspect, multi-permutations, are provided. The paradigm of representing information with permutations is generalized to the case where the number of cells in each level is a constant greater than one.Type: GrantFiled: August 10, 2015Date of Patent: May 30, 2017Assignee: California Institute of TechnologyInventors: Anxiao Jiang, Eyal En Gad, Jehoshua Bruck
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Publication number: 20160335156Abstract: Techniques are disclosed for generating codes for representation of data in memory devices that may avoid the block erasure operation in changing data values. Data values comprising binary digits (bits) can be encoded and decoded using the generated codes, referred to as codewords, such that the codewords may comprise a block erasure-avoiding code, in which the binary digits of a data message m can be encoded such that the encoded data message can be stored into multiple memory cells of a data device and, once a memory cell value is changed from a first logic value to a second logic value, the value of the memory cell may remain at the second logic value, regardless of subsequently received messages, until a block erasure operation on the memory cell.Type: ApplicationFiled: January 14, 2015Publication date: November 17, 2016Applicants: California Institute of Technology, New Jersey Institute of Technology, SUNY at Buffalo, Texas A&M UniversityInventors: Eyal En Gad, Yue Li, Joerg Kliewer, Michael Langberg, Anxiao Jiang, Jehoshua Bruck
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Publication number: 20160170684Abstract: Rank modulation has been recently proposed as a scheme for storing information in flash memories. Three improved aspects are disclosed. In one aspect the minimum push-up scheme, for storing data in flash memories is provided. It aims at minimizing the cost of changing the state of the memory. In another aspect, multi-cells, used for storing data in flash memories is provided. Each transistor is replaced with a multi-cell of m transistors connected in parallel. In yet another aspect, multi-permutations, are provided. The paradigm of representing information with permutations is generalized to the case where the number of cells in each level is a constant greater than one.Type: ApplicationFiled: August 10, 2015Publication date: June 16, 2016Inventors: Anxiao Jiang, Eyal En Gad, Jehoshua Bruck
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Publication number: 20160170672Abstract: The reliability of NAND flash memory decreases rapidly as density increases, preventing the wide adoptions of flash-based storage systems. A novel data representation scheme named rank modulation (RM) is discussed for improving NAND flash reliability. RM encodes data using the relative orders of memory cell voltages, which is inherently resilient to asymmetric errors. For studying the effectiveness of RM in flash, RM is adapted to make it simple to implement with existing flash memories. The implementation is evaluated under different types of noise of 20 nm flash memory. Results show that RM offers significantly lower cell error rates compared to the current data representation in flash at typical P/E cycles. RM is applied to flash-based archival storage and shows that RM brings up to six times longer data retention time for 16 nm flash memory.Type: ApplicationFiled: December 10, 2015Publication date: June 16, 2016Inventors: Yue Li, Eyal En Gad, Anxiao Jiang, Jehoshua Bruck
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Patent number: 9230652Abstract: Rank modulation has been recently proposed as a scheme for storing information in flash memories. Three improved aspects are disclosed. In one aspect the minimum push-up scheme, for storing data in flash memories is provided. It aims at minimizing the cost of changing the state of the memory. In another aspect, multi-cells, used for storing data in flash memories is provided. Each transistor is replaced with a multi-cell of mm transistors connected in parallel. In yet another aspect, multi-permutations, are provided. The paradigm of representing information with permutations is generalized to the case where the number of cells in each level is a constant greater than one.Type: GrantFiled: March 8, 2013Date of Patent: January 5, 2016Assignee: California Institute of TechnologyInventors: Anxiao Jiang, Eyal En Gad, Jehoshua Bruck
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Publication number: 20150324253Abstract: Rank modulation has been recently proposed as a scheme for storing information in flash memories. Three improved aspects are disclosed. In one aspect the minimum push-up scheme, for storing data in flash memories is provided. It aims at minimizing the cost of changing the state of the memory. In another aspect, multi-cells, used for storing data in flash memories is provided. Each transistor is replaced with a multi-cell of mm transistors connected in parallel. In yet another aspect, multi-permutations, are provided. The paradigm of representing information with permutations is generalized to the case where the number of cells in each level is a constant greater than one. In yet another aspect, rank-modulation rewriting schemes which take advantage of polar codes, are provided for use with flash memory.Type: ApplicationFiled: June 2, 2015Publication date: November 12, 2015Inventors: Anxiao Jiang, Eyal En Gad, Jehoshua Bruck, Eitan Yaakobi
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Publication number: 20150293716Abstract: Both rewriting and error correction are technologies usable for non-volatile memories, such as flash memories. A coding scheme is disclosed herein that combines rewriting and error correction for the write-once memory model. In some embodiments, code construction is based on polar codes, and supports any number of rewrites and corrects a substantial number of errors. The code may be analyzed for a binary symmetric channel. The results can be extended to multi-level cells and more general noise models.Type: ApplicationFiled: July 5, 2013Publication date: October 15, 2015Applicant: Texas A&M University SystemInventors: Anxiao Jiang, Yue Li, Eyal En Gad, Michael Langberg, Jehoshua Bruck
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Patent number: 9086955Abstract: Rank modulation has been recently proposed as a scheme for storing information in flash memories. Three improved aspects are disclosed. In one aspect the minimum push-up scheme, for storing data in flash memories is provided. It aims at minimizing the cost of changing the state of the memory. In another aspect, multi-cells, used for storing data in flash memories is provided. Each transistor is replaced with a multi-cell of mm transistors connected in parallel. In yet another aspect, multi-permutations, are provided. The paradigm of representing information with permutations is generalized to the case where the number of cells in each level is a constant greater than one. In yet another aspect, rank-modulation rewriting schemes which take advantage of polar codes, are provided for use with flash memory.Type: GrantFiled: March 8, 2013Date of Patent: July 21, 2015Assignees: California Institute of Technology, Texas A&M University SystemInventors: Anxiao Jiang, Eyal En Gad, Jehoshua Bruck, Eitan Yaakobi
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Patent number: 8780620Abstract: A memory device having a plurality of cells, each of which stores a value, where the values of the cells are mapped to discrete levels and the discrete levels represent data, is programmed by determining a maximum number of cell levels in the memory device, and determining the set of values that are associated with each of the cell levels. The maximum number of cell levels for the memory device is determined by an adaptive programming system connected to the memory device, based on a plurality of cell values attained by at least one cell of the memory device, in response to voltage applied by the adaptive programming system to the cells of the memory device. The adaptive programming system associates, for each of the cell levels, a different set of cell values of the plurality of cell values attained by the cells to which voltage is applied.Type: GrantFiled: September 20, 2011Date of Patent: July 15, 2014Assignees: The Texas A&M University, California Institute of TechnologyInventors: Anxiao Jiang, Bruck Jehoshua, Zhiying Wang, HongChao Zhou
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Publication number: 20130268723Abstract: Rank modulation has been recently proposed as a scheme for storing information in flash memories. Three improved aspects are disclosed. In one aspect the minimum push-up scheme, for storing data in flash memories is provided. It aims at minimizing the cost of changing the state of the memory. In another aspect, multi-cells, used for storing data in flash memories is provided. Each transistor is replaced with a multi-cell of mm transistors connected in parallel. In yet another aspect, multi-permutations, are provided. The paradigm of representing information with permutations is generalized to the case where the number of cells in each level is a constant greater than one.Type: ApplicationFiled: March 8, 2013Publication date: October 10, 2013Inventors: Anxiao Jiang, Eyal En Gad, Jehoshua Bruck
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Publication number: 20130254466Abstract: Rank modulation has been recently proposed as a scheme for storing information in flash memories. Three improved aspects are disclosed. In one aspect the minimum push-up scheme, for storing data in flash memories is provided. It aims at minimizing the cost of changing the state of the memory. In another aspect, multi-cells, used for storing data in flash memories is provided. Each transistor is replaced with a multi-cell of mm transistors connected in parallel. In yet another aspect, multi-permutations, are provided. The paradigm of representing information with permutations is generalized to the case where the number of cells in each level is a constant greater than one. In yet another aspect, rank-modulation rewriting schemes which take advantage of polar codes, are provided for use with flash memory.Type: ApplicationFiled: March 8, 2013Publication date: September 26, 2013Applicants: TEXAS A&M UNIVERSITY SYSTEM, CALIFORNIA INSTITUTE OF TECHNOLOGYInventors: Anxiao Jiang, Eyal En Gad, Jehoshua Bruck, Eitan Yaakobi
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Patent number: 8245094Abstract: We investigate a novel storage technology, Rank Modulation, for flash memories. In this scheme, a set of n cells stores information in the permutation induced by the different charge levels of the individual cells. The resulting scheme eliminates the need for discrete cell levels, and overshoot errors when programming cells (a serious problem that reduces the writing speed), as well as mitigate the problem of asymmetric errors. We present schemes for Gray codes, rewriting and joint coding in the rank modulation paradigm.Type: GrantFiled: November 20, 2008Date of Patent: August 14, 2012Assignee: California Institute of Technology Texas A & MInventors: Anxiao Jiang, Robert Mateescu, Moshe Schwartz, Jehoshua Bruck
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Patent number: 8225180Abstract: We investigate error-correcting codes for a novel storage technology, which we call the rank-modulation scheme. In this scheme, a set of n cells stores information in the permutation induced by the different levels of the individual cells. The resulting scheme eliminates the need for discrete cell levels, and overshoot errors when programming cells (a serious problem that reduces the writing speed), as well as mitigates the problem of asymmetric errors. In this discussion, the properties of error correction in rank modulation codes are studied. We show that the adjacency graph of permutations is a subgraph of a multi-dimensional array of a special size, a property that enables code designs based on Lee-metric codes and L1-metric codes. We present a one-error-correcting code whose size is at least half of the optimal size. We also present additional error-correcting codes and some related bounds.Type: GrantFiled: November 20, 2008Date of Patent: July 17, 2012Assignees: California Institute of Technology, Texas A&M University SystemInventors: Anxiao Jiang, Moshe Schwartz, Jehoshua Bruck
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Publication number: 20120096234Abstract: A memory device having a plurality of cells, each of which stores a value, where the values of the cells are mapped to discrete levels and the discrete levels represent data, is programmed by determining a maximum number of cell levels in the memory device, and determining the set of values that are associated with each of the cell levels. The maximum number of cell levels for the memory device is determined by an adaptive programming system connected to the memory device, based on a plurality of cell values attained by at least one cell of the memory device, in response to voltage applied by the adaptive programming system to the cells of the memory device. The adaptive programming system associates, for each of the cell levels, a different set of cell values of the plurality of cell values attained by the cells to which voltage is applied.Type: ApplicationFiled: September 20, 2011Publication date: April 19, 2012Applicants: The Texas A&M University, California Institute of TechnologyInventors: Anxiao Jiang, Bruck Jehoshua, Zhiying Wang, HongChao Zhou
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Patent number: 7752332Abstract: Routing in a wireless network of communication devices that are located within a network boundary moves network traffic from a first communication device to a second communication device. A geometric indicator of network connectivity is constructed that identifies a curve on which network nodes are located and a network location for each node of the wireless network is determined, so that the network location of a node p identifies a node on the geometric indicator curve that is closest to the node p and indicates connectivity from the node p to the closest node of the geometric indicator curve. A routing scheme is determined, to route in the wireless network from the first communication device to the second communication device based on the respective determined network locations for the first and second communication devices.Type: GrantFiled: April 18, 2006Date of Patent: July 6, 2010Assignee: California Institute of TechnologyInventors: Anxiao Jiang, Jie Gao, Jehoshua Bruck