Abstract: The present disclosure provides a stacked nanosheet gate-all-around device with an air spacer and a manufacturing method. The device includes: a substrate, where a first dielectric layer is on the substrate, a gap array is in the first dielectric layer, the gap array includes multiple gap units, and each gap unit is in a fin shape above the substrate; a nanosheet stacking portion above the gap unit, including a stack formed by multiple nanosheets, and the stack formed by the nanosheets constitutes multiple conductive channels; a gate-all-around surrounding the nanosheet stacking portion; and a source/drain region on two opposite sides of the nanosheet stacking portion, where an empty spacer is between the source/drain region and the gate-all-around. An interior of the gap array and an interior of the empty spacer are filled with at least one of air, a reducing gas, or an inert gas.

Abstract: The present disclosure relates to a stacked nanosheet gate-all-around device with an air spacer and a method of manufacturing a stacked nanosheet gate-all-around device with an air spacer. The stacked nanosheet gate-all-around device with the air spacer includes: a substrate with a shallow trench isolation structure on a surface of the substrate; a nanosheet stacking portion provided above the substrate, where the nanosheet stacking portion includes a stack formed by a plurality of nanosheets, and the stack formed by the nanosheets constitutes a plurality of conductive channels; a gate-all-around surrounding the nanosheet stacking portion; and a source/drain region located on two opposite sides of the nanosheet stacking portion, where an empty spacer is provided between the source/drain region and the gate-all-around, where an interior of the empty spacer is filled with at least one of air, a reducing gas, or an inert gas.

Abstract: An embodiment of the present disclosure provides an etching method, having the following steps: forming a modified layer having a thickness of one or several atom layers on a selected region of a surface of a semiconductor material layer by using a modifier; and removing the modified layer. When a semiconductor is processed, this method achieves precise control over the etching thickness and improves the etching rate at the same time.

Abstract: An embodiment of the present disclosure provides an etching method, having the following steps: forming a modified layer having a thickness of one or several atom layers on a selected region of a surface of a semiconductor material layer by using a modifier; and removing the modified layer. When a semiconductor is processed, this method achieves precise control over the etching thickness and improves the etching rate at the same time.

Abstract: An embodiment of the present disclosure provides an etching method, having the following steps: forming a modified layer having a thickness of one or several atom layers on a selected region of a surface of a semiconductor material layer by using a modifier; and removing the modified layer. When a semiconductor is processed, this method achieves precise control over the etching thickness and improves the etching rate at the same time.

Abstract: An embodiment of the present disclosure provides an etching method, having the following steps: forming a modified layer having a thickness of one or several atom layers on a selected region of a surface of a semiconductor material layer by using a modifier; and removing the modified layer. When a semiconductor is processed, this method achieves precise control over the etching thickness and improves the etching rate at the same time.

Abstract: The disclosure provides a semiconductor device, a manufacturing method thereof, and an electronic device including the device. The semiconductor device includes: a substrate, the substrate being a silicon substrate or an SOI substrate; a SiGe Fin formed on the substrate, wherein the SiGe Fin is a sandwich-like SixGe1-x/SiyGe1-y/SizGe1-z structure with different Ge contents in the horizontal direction, where x is 0.05˜0.95, y is 0.1˜0.9, and z is 0.05˜0.95; and a shallow trench isolation region disposed on the substrate and adjacent to all sides of the SiGe Fin, wherein a top surface of the SiGe Fin facing away from the substrate protrudes from the shallow trench isolation region. The disclosure proposes a device structure of a sandwich-like SixGe1-x/SiyGe1-y/SizGe1-z Fin structure with different Ge contents, which can adjust the Ge content to change the band gap, thereby adjusting the threshold, and improving electrical properties such as mobility (effective mass change) and leakage.