Abstract: The present document discloses circuits and methods for providing an output voltage at an output port. In one of the embodiments, a circuit has a power amplifier having an output. In particular, the circuit may have a first transformer including a first coil and a second coil. Moreover, the circuit may have a first capacitor connected in parallel to the first coil and a second capacitor connected in parallel to the second coil. More particularly, the circuit may be adapted to have a first end of the first coil connected to the output of the power amplifier, and a second end of the first coil connected to the output port of the circuit.

Abstract: A switched-capacitor power amplifier comprising a plurality of cells and methods for its operation are described. Switched signal lines switch supply to respective capacitors. Switches connect respective signal lines to a first supply and switches connect respective signal lines to a second supply. Pairs of switches on each signal line are switched so that one is switched off whilst the other is switched on. In a “full amplitude” mode, operation of the switches provides an output having a peak determined by the first supply. A switch signal line is provided between nodes in respective signal lines, a switch being provided in the switch signal line. In a “half amplitude” mode, switch is switched at the radio frequency in the other direction to that of switches connecting the signal lines to respective ones of the first and second supplies with the other switches being kept open.

Abstract: A digital power amplification circuit includes a decoding block configured to receive a first stream of digital codes and to derive from the first stream a second stream of digital codes, the decoding block including a decoder configured to decode the digital codes of the first stream and the second stream at a first clock rate, a main digital power amplifier configured to receive the decoded digital codes of the first stream, an upsampler configured to upsample the decoded digital codes of the second stream to a second clock rate that is greater than the first clock rate, an auxiliary digital power amplifier configured to receive the decoded digital codes of the second stream upsampled to the second clock rate, and a summer configured to sum (i) a main output signal of the main digital power amplifier and (ii) an auxiliary output signal of the auxiliary digital power amplifier.

Abstract: A digital power amplification circuit includes a decoding block configured to receive a first stream of digital codes and to derive from the first stream a second stream of digital codes, the decoding block including a decoder configured to decode the digital codes of the first stream and the second stream at a first clock rate, a main digital power amplifier configured to receive the decoded digital codes of the first stream, an upsampler configured to upsample the decoded digital codes of the second stream to a second clock rate that is greater than the first clock rate, an auxiliary digital power amplifier configured to receive the decoded digital codes of the second stream upsampled to the second clock rate, and a summer configured to sum (i) a main output signal of the main digital power amplifier and (ii) an auxiliary output signal of the auxiliary digital power amplifier.

Abstract: A switched-capacitor power amplifier comprising a plurality of cells and methods for its operation are described. Switched signal lines switch supply to respective capacitors. Switches connect respective signal lines to a first supply and switches connect respective signal lines to a second supply. Pairs of switches on each signal line are switched so that one is switched off whilst the other is switched on. In a “full amplitude” mode, operation of the switches provides an output having a peak determined by the first supply. A switch signal line is provided between nodes in respective signal lines, a switch being provided in the switch signal line. In a “half amplitude” mode, switch is switched at the radio frequency in the other direction to that of switches connecting the signal lines to respective ones of the first and second supplies with the other switches being kept open.

Abstract: The present disclosure relates to a circuit that includes an input port for applying a sinusoidal input signal, and a first buffering means for converting the sinusoidal input signal into a square wave signal. A DC level of the square wave signal may be defined by an adjustable threshold voltage level. The circuit also includes an output port for outputting the square wave signal to a power amplifier. Further, the circuit includes a feedback loop having a low pass filtering means arranged for filtering the square wave signal and comparing means arranged for comparing a DC level of a filtered signal received from the low pass filtering means with a pre-set reference level. The reference level may be selected for cancelling a given harmonic component. The comparing means is further arranged for outputting to the first buffering means a correction signal for adjusting the threshold voltage level of the first buffering means.

Abstract: The present disclosure relates to a circuit that includes an input port for applying a sinusoidal input signal, and a first buffering means for converting the sinusoidal input signal into a square wave signal. A DC level of the square wave signal may be defined by an adjustable threshold voltage level. The circuit also includes an output port for outputting the square wave signal to a power amplifier. Further, the circuit includes a feedback loop having a low pass filtering means arranged for filtering the square wave signal and comparing means arranged for comparing a DC level of a filtered signal received from the low pass filtering means with a pre-set reference level. The reference level may be selected for cancelling a given harmonic component. The comparing means is further arranged for outputting to the first buffering means a correction signal for adjusting the threshold voltage level of the first buffering means.