Abstract: The present disclosure provides technical solutions related to intelligent cloud management based on profile. Artificial intelligent is applied to cloud management and cloud management suggestion may be proposed intelligently. In daily work, behaviors in using cloud resources may show characteristics of cloud users or cloud tenants themselves. The technical solution of intelligent cloud management of the present disclosure generates profile identifying cloud using characteristics by extracting behavior data in using cloud and intelligently proposes cloud management suggestions based on the profile.

Abstract: The present disclosure provides technical solutions related to action undo service based on cloud platform. Related operations dependent on target operations to be undone may be obtained by dependency analysis and the target operations and the related operations may be undone by time sequence so as to reduce the conflict caused by the undo operations.

Abstract: A device structure for reducing FinFET parasitic resistance and a manufacturing method thereof.

Abstract: A method and system for testing optimization and molding optimization of semiconductor devices. The testing optimization method is executed based on a test structure for testing the specific non-direct-current parameters, constructing an auxiliary structure of the test structure and testing the non-direct-current parameter, calculating the parallel parasitic resistance and the series parasitic resistance of the test structure based on the parasitic network model and the testing result of the auxiliary structure; performing linear fitting on the parallel parasitic resistance and the series parasitic resistance; and performing a direct-current testing on the test structure to obtain direct-current testing data and correcting the direct-current testing data based on the direct-current equivalent sub-circuit model.

Abstract: A manufacturing method is provided for fabricating a vertical channel gate-all-around MOSFET by epitaxy processes. The method includes growing a first epitaxial layer on a top semiconducting layer of a substrate; etching the first epitaxial layer and the top layer to form a first source/drain pattern in the top layer; etching the first epitaxial layer to form a vertical channel structure; then forming a gate dielectric layer on the vertical channel structure surface; forming a sandwich structure composed of a bottom spacer layer, a gate electrode layer and a top spacer layer; etching the top spacer layer and the gate electrode layer to form a gate pattern followed by forming a top spacer structure thereon; growing a second epitaxial layer and etching to form a second source/drain pattern.

Abstract: A manufacturing method is provided for fabricating a vertical channel gate-all-around MOSFET by epitaxy processes. The method includes growing a first epitaxial layer on a top semiconducting layer of a substrate; etching the first epitaxial layer and the top layer to form a first source/drain pattern in the top layer; etching the first epitaxial layer to form a vertical channel structure; then forming a gate dielectric layer on the vertical channel structure surface; forming a sandwich structure composed of a bottom spacer layer, a gate electrode layer and a top spacer layer; etching the top spacer layer and the gate electrode layer to form a gate pattern followed by forming a top spacer structure thereon; growing a second epitaxial layer and etching to form a second source/drain pattern.