Patents by Inventor Ao HU

Ao HU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Hardware accelerator for hypergraph processing and operating method thereof
    Patent number: 12339775
    Abstract: The present invention relates to a hardware accelerator for hypergraph processing and its operating method, the hardware accelerator comprising: a data loader: for, in the presence of a data-centric load-trigger-reduce execution model, reading hypergraph partition data from an off-chip memory successively according to hypergraph data structure and an order of hypergraph partitions; an address translator, for deploying the hypergraph data into a private register of a processor and/or into a buffer memory according to a priority level of loaded data, and recording corresponding offset information; a task trigger, for generating computing tasks according to the loaded data, and scheduling the computing tasks into the processor; the processor, for receiving and executing the computing tasks; a reducer, for scheduling intermediate results into a first-priority-data reducer unit or a second-priority-data reducer unit depending on the priority level of the data so as to execute a reducing operation for the intermedi
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: June 24, 2025
    Assignees: Huazhong University of Science and Technology, Zhejiang Lab
    Inventors: Long Zheng, Qinggang Wang, Xiaofei Liao, Ao Hu, Hai Jin
  • HARDWARE ACCELERATOR FOR HYPERGRAPH PROCESSING AND OPERATING METHOD THEREOF
    Publication number: 20240061779
    Abstract: The present invention relates to a hardware accelerator for hypergraph processing and its operating method, the hardware accelerator comprising: a data loader: for, in the presence of a data-centric load-trigger-reduce execution model, reading hypergraph partition data from an off-chip memory successively according to hypergraph data structure and an order of hypergraph partitions; an address translator, for deploying the hypergraph data into a private register of a processor and/or into a buffer memory according to a priority level of loaded data, and recording corresponding offset information; a task trigger, for generating computing tasks according to the loaded data, and scheduling the computing tasks into the processor; the processor, for receiving and executing the computing tasks; a reducer, for scheduling intermediate results into a first-priority-data reducer unit or a second-priority-data reducer unit depending on the priority level of the data so as to execute a reducing operation for the intermedi
    Type: Application
    Filed: December 22, 2022
    Publication date: February 22, 2024
    Inventors: Long ZHENG, Qinggang WANG, Xiaofei LIAO, Ao HU, Hai JIN
  • Dehumidifier
    Patent number: D1074965
    Type: Grant
    Filed: April 23, 2024
    Date of Patent: May 13, 2025
    Inventors: Yunfei Du, Jinsong Duan, Jiayuan Wang, Ao Hu