Abstract: A memory disposition device of a computer system in which a plurality of nodes exists, each of the nodes including a pair of a processor and a memory, the memory disposition device includes: at least one memory configured to store instructions; and at least one processor configured to execute the instructions to: determine a node in which a memory area to be mapped is disposed; and duplicate the memory area and disposing the memory area, based on a determination result, in a local memory of a node in which a process operates, wherein the at least one processor is configured to invalidate maintenance of cache coherency between the nodes and invalidates access to a remote memory for the process.

Abstract: A main processor core having a first memory and a sub processor core having a second memory and controlled by the main processor core are included. An operating system is incorporated in the main processor core, and no operating system is incorporated in the sub processor core. Shared memories are formed in the first and second memories, respectively. Data in the shared memories of the first and second memories are synchronized. The main processor core is configured to synchronize the data in the shared memories formed in the first and second memories while the sub processor core stops operating.

Abstract: A control apparatus includes: an external apparatus control unit configured to load data necessary for execution of calculation processing onto an external memory included by an external apparatus and also cause the external apparatus to execute the calculation processing; a memory access unit configured to convert a logical address used in the calculation processing into a physical address and also access the external memory on the basis of the converted physical address; and an external memory virtualizing unit configured to virtualize the external memory by associating the converted physical address with an external memory physical address that is a physical address in the external memory.

Abstract: A control apparatus includes: an external apparatus control unit configured to load data necessary for execution of calculation processing onto an external memory included by an external apparatus and also cause the external apparatus to execute the calculation processing; a memory access unit configured to convert a logical address used in the calculation processing into a physical address and also access the external memory on the basis of the converted physical address; and an external memory virtualizing unit configured to virtualize the external memory by associating the converted physical address with an external memory physical address that is a physical address in the external memory.

Abstract: A main processor core having a first memory and a sub processor core having a second memory and controlled by the main processor core are included. An operating system is incorporated in the main processor core, and no operating system is incorporated in the sub processor core. Shared memories are formed in the first and second memories, respectively. Data in the shared memories of the first and second memories are synchronized. The main processor core is configured to synchronize the data in the shared memories formed in the first and second memories while the sub processor core stops operating.