Patents by Inventor Apama Iyer

Apama Iyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150037915
    Abstract: In embodiments, a method of laser scribing a mask disposed over a semiconductor wafer includes determining a height of the semiconductor over which a mask layer is disposed prior to laser scribing the mask layer. In one embodiment the method includes: determining a height of the semiconductor wafer under the mask in a dicing street using an optical sensor and patterning the mask with a laser scribing process. The laser scribing process focuses a scribing laser beam at a plane corresponding to the determined height of the semiconductor wafer in the dicing street. Examples of determining the height of the semiconductor wafer can include directing a laser beam to the dicing street of the semiconductor wafer, which is transmitted through the mask and reflected from the wafer, and identifying an image on a surface of the wafer under the mask with a camera.
    Type: Application
    Filed: September 24, 2013
    Publication date: February 5, 2015
    Inventors: Wei-Sheng LEI, Brad Eaton, Apama IYER, Madhava Rao Yalamanchili, Ajay Kumar
  • Patent number: 8883614
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, approaches for wafer dicing with wide kerf by using a laser scribing and plasma etching hybrid approach are described. For example, a method of dicing a semiconductor wafer including a plurality of integrated circuits separated by dicing streets involves forming a mask above the semiconductor wafer, the mask having a layer covering and protecting the integrated circuits. The method also involves patterning the mask with a laser scribing process to provide a patterned mask having a pair of parallel gaps for each dicing street, exposing regions of the semiconductor wafer between the integrated circuits. Each gap of each pair of parallel gaps is separated by a distance. The method also involves etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: November 11, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Brad Eaton, Apama Iyer, Madhava Rao Yalamanchili, Ajay Kumar