Abstract: A method for designing a decision feedback equalizer (DFE) that handles packet based input data signals uses an inter symbol interference (ISI) removal loop and an inter chip interference (ICI) removal loop which is nested inside the ISI loop, for maximum interference removal and limited error propagation. The DFE may use a feed forward filter and a series connected chip-flow control buffer for receiving the input data signals. The DFE of the invention has application in 802.11 b PHY and 802.11 g PHY scenarios and any application involving a DFE with the need for minimum error propagation. Taught herein is a combined weighted DFE with erasure provision and interference removal in an optional two step mechanism. An article comprising a computer storage medium to execute the DFE design method is also disclosed.