Patents by Inventor Aparna Ramachandran

Aparna Ramachandran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods and circuits for balancing bitline precharge
    Publication number: 20040151044
    Abstract: A memory array design is provided. Memory cells are defined an intersections of rows and columns. A pair of bitline segments are defined for each column. A connecting load device of each memory cell is connected to either a first or a second of the pair of bitline segments. An equal number of load devices in each column couple to each of the pair of bitlines.
    Type: Application
    Filed: January 30, 2003
    Publication date: August 5, 2004
    Applicant: Sun Microsystems, Inc.
    Inventors: Shree Kant, Aparna Ramachandran, Ranjan Vaish
  • Low power memory design with asymmetric bit line driver
    Patent number: 6707721
    Abstract: A register file design having an asymmetric bit line driver is provided. More specifically, the register file design uses a memory element that has a footer device that facilitates the discharge/charging of a bit line through a pass device, where a width of the footer device is greater than a width of the pass device. Further, a method for performing low power memory operations using asymmetric bit line drivers is provided.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: March 16, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Gajendra Singh, Aparna Ramachandran, Miao Rao, Shree Kant
  • High performance address decode technique for arrays
    Patent number: 6646951
    Abstract: An address decoder having pre-decode logic circuitry positioned in between ends of final decode logic circuitry is provided. Such an address decoder yields less wire load, less gate load, less power consumption, and increased speed due to the pre-decode logic circuitry having to be capable of only driving a signal over half the length of a final decoder. Further, a method to select memory elements from a memory array using centrally positioned pre-decode logic circuitry is provided.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: November 11, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: Shree Kant, Aparna Ramachandran
  • Low power memory design with asymmetric bit line driver
    Publication number: 20030174535
    Abstract: A register file design having an asymmetric bit line driver is provided. More specifically, the register file design uses a memory element that has a footer device that facilitates the discharge/charging of a bit line through a pass device, where a width of the footer device is greater than a width of the pass device. Further, a method for performing low power memory operations using asymmetric bit line drivers is provided.
    Type: Application
    Filed: March 13, 2002
    Publication date: September 18, 2003
    Inventors: Gajendra Singh, Aparna Ramachandran, Miao Rao, Shree Kant
  • High performance address decode technique for arrays
    Publication number: 20030076732
    Abstract: An address decoder having pre-decode logic circuitry positioned in between ends of final decode logic circuitry is provided. Such an address decoder yields less wire load, less gate load, less power consumption, and increased speed due to the pre-decode logic circuitry having to be capable of only driving a signal over half the length of a final decoder. Further, a method to select memory elements from a memory array using centrally positioned pre-decode logic circuitry is provided.
    Type: Application
    Filed: October 23, 2001
    Publication date: April 24, 2003
    Inventors: Shree Kant, Aparna Ramachandran