Patents by Inventor Apostolos Voutsas
Apostolos Voutsas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11667111Abstract: Display modules typically incorporate a transparent hard material such as glass on the outside of the module in order to better protect the display stack from scratches, dents, and other mechanical deformations. However, as displays move to novel form factors such as bendable, foldable, and reliable display modules, these transparent hard materials (e.g., glass) may not be used due to their limited flexibility. Therefore, it is desirable that replacement materials be sufficiently flexible while maintaining the desirable optical (e.g., >90% transmission and low yellow index) and mechanical properties (e.g., pencil hardness>H) that comparable glass hard materials offer.Type: GrantFiled: June 19, 2018Date of Patent: June 6, 2023Assignee: Ares Materials Inc.Inventors: Radu Reit, Adrian Avendano-Bolivar, Apostolos Voutsas, David Arreaga-Salas
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Patent number: 11427684Abstract: Provided is a method for forming an organic planarization layer. The method includes forming lithographically-patterned arrays atop a substrate; disposing a thiol-based photocurable resin on to the lithographically-patterned arrays to form a photocurable planarization layer; and curing the photocurable planarization layer to form a flat surface above the lithographically-patterned array.Type: GrantFiled: June 20, 2018Date of Patent: August 30, 2022Assignee: Ares Materials, Inc.Inventors: Radu Reit, Adrian Avendano-Bolivar, Apostolos Voutsas, David Arreaga-Salas
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Publication number: 20210147631Abstract: Provided is a method for forming an organic planarization layer. The method includes forming lithographically-patterned arrays atop a substrate; disposing a thiol-based photocurable resin on to the lithographically-patterned arrays to form a photocurable planarization layer; and curing the photocurable planarization layer to form a flat surface above the lithographically-patterned array.Type: ApplicationFiled: June 20, 2018Publication date: May 20, 2021Inventors: Radu REIT, Adrian AVENDANO-BOLIVAR, Apostolos VOUTSAS, David ARREAGA-SALAS
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Publication number: 20200255709Abstract: Provided are semi -interpenetrating optically clear adhesives, methods of use, and methods of manufacture. An example semi-interpenetrating optically clear adhesive comprises a transparent polymer network comprised of at least two or more interpenetrating polymer networks, wherein at least one polymer network is a thermoset material and at least one other polymer network is a thermoplastic material, yielding an optically clear adhesive with a transparency above 80% and an elastic toughness above 1 MJ/m3.Type: ApplicationFiled: October 17, 2017Publication date: August 13, 2020Inventors: Radu REIT, Jesus Espinoza DIAZ, Adrian AVENDANO-BOLIVAR, Apostolos VOUTSAS, David ARREAGA-SALAS
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Publication number: 20200123410Abstract: Display modules typically incorporate a transparent hard material such as glass on the outside of the module in order to better protect the display stack from scratches, dents, and other mechanical deformations. However, as displays move to novel form factors such as bendable, foldable, and reliable display modules, these transparent hard materials (e.g., glass) may not be used due to their limited flexibility. Therefore, it is desirable that replacement materials be sufficiently flexible while maintaining the desirable optical (e.g., >90% transmission and low yellow index) and mechanical properties (e.g., pencil hardness >H) that comparable glass hard materials offer.Type: ApplicationFiled: June 19, 2018Publication date: April 23, 2020Inventors: Radu REIT, Adrian AVENDANO-BOLIVAR, Apostolos VOUTSAS, David ARREAGA-SALAS
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Publication number: 20160336350Abstract: A circuit-on-wire (CoW) is provided that is made from a flexible metal wire with an outer surface, and a plurality of discrete electrical control devices formed in series along the metal wire outer surface. Each control device may have an electrical contact accessible through the metal wire. In one aspect, the control device may have a via through the metal wire from the top surface to the bottom surface with a second electrical contact accessible through the via. In addition, the control devices may have a top surface with an accessible third electrical contact. For example, the control device may be a first thin-film transistor (TFT), with a gate electrode accessible through the metal wire, wherein the second electrical contact is a first source/drain (S/D) electrode, and wherein the third electrical contact is a second S/D electrode. Using the above-described CoW, a woven active matrix array can be fabricated.Type: ApplicationFiled: July 25, 2016Publication date: November 17, 2016Inventors: Apostolos Voutsas, Themistokles Afentakis
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Patent number: 9425221Abstract: A circuit-on-wire (CoW) is provided that is made from a flexible metal wire with an outer surface, and a plurality of discrete electrical control devices formed in series along the metal wire outer surface. Each control device may have an electrical contact accessible through the metal wire. In one aspect, the control device may have a via through the metal wire from the top surface to the bottom surface with a second electrical contact accessible through the via. In addition, the control devices may have a top surface with an accessible third electrical contact. For example, the control device may be a first thin-film transistor (TFT), with a gate electrode accessible through the metal wire, wherein the second electrical contact is a first source/drain (S/D) electrode, and wherein the third electrical contact is a second S/D electrode. Using the above-described CoW, a woven active matrix array can be fabricated.Type: GrantFiled: January 31, 2014Date of Patent: August 23, 2016Assignee: Sharp Laboratories of America, Inc.Inventors: Apostolos Voutsas, Themistokles Afentakis
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Publication number: 20160172562Abstract: A method is provided for forming a circuit-on-wire (CoW) assembly. The method forms a flexible line with a plurality of periodic alignment marks used as a guide to place CoW devices overlying a surface of the flexible line. The CoW devices may be LEDs, capacitors, diodes, photodiodes, resistors, thin-film transistors, or combinations of the above-listed elements. The flexible line may be a conductive material, such as a metal wire, and the periodic alignment marks may be vias formed through the wire. If the flexible line is electrically conductive, an electrically conductive adhesive may be applied to the electrically conductive line, so that an electrical connection is formed between the CoW devices and the electrically conductive line. Subsequent to placing the CoW devices, proccesses may be formed on the flexible line and CoW devices such as lithographic etching and thin-film deposition. An active matrix array using CoW devices is also presented.Type: ApplicationFiled: February 22, 2016Publication date: June 16, 2016Inventor: Apostolos Voutsas
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Patent number: 9299725Abstract: A method is provided for forming a circuit-on-wire (CoW) assembly. The method forms a flexible line with a plurality of periodic alignment marks used as a guide to place CoW devices overlying a surface of the flexible line. The CoW devices may be LEDs, capacitors, diodes, photodiodes, resistors, thin-film transistors, or combinations of the above-listed elements. The flexible line may be a conductive material, such as a metal wire, and the periodic alignment marks may be vias formed through the wire. If the flexible line is electrically conductive, an electrically conductive adhesive may be applied to the electrically conductive line, so that an electrical connection is formed between the CoW devices and the electrically conductive line. Subsequent to placing the CON devices, processes may be formed on the flexible line and CoW devices such as lithographic etching and thin-film deposition. An active matrix array using CoW devices is also presented.Type: GrantFiled: April 18, 2014Date of Patent: March 29, 2016Assignee: Sharp Laboratories of America, Inc.Inventor: Apostolos Voutsas
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Publication number: 20150221671Abstract: A method is provided for forming a circuit-on-wire (CoW) assembly. The method forms a flexible line with a plurality of periodic alignment marks used as a guide to place CoW devices overlying a surface of the flexible line. The CoW devices may be LEDs, capacitors, diodes, photodiodes, resistors, thin-film transistors, or combinations of the above-listed elements. The flexible line may be a conductive material, such as a metal wire, and the periodic alignment marks may be vias formed through the wire. If the flexible line is electrically conductive, an electrically conductive adhesive may be applied to the electrically conductive line, so that an electrical connection is formed between the CoW devices and the electrically conductive line. Subsequent to placing the CON devices, processes may be formed on the flexible line and CoW devices such as lithographic etching and thin-film deposition. An active matrix array using CoW devices is also presented.Type: ApplicationFiled: April 18, 2014Publication date: August 6, 2015Applicant: Sharp Laboratories of America, Inc.Inventor: Apostolos Voutsas
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Publication number: 20150221682Abstract: A circuit-on-wire (CoW) is provided that is made from a flexible metal wire with an outer surface, and a plurality of discrete electrical control devices formed in series along the metal wire outer surface. Each control device may have an electrical contact accessible through the metal wire. In one aspect, the control device may have a via through the metal wire from the top surface to the bottom surface with a second electrical contact accessible through the via. In addition, the control devices may have a top surface with an accessible third electrical contact. For example, the control device may be a first thin-film transistor (TFT), with a gate electrode accessible through the metal wire, wherein the second electrical contact is a first source/drain (S/D) electrode, and wherein the third electrical contact is a second S/D electrode. Using the above-described CoW, a woven active matrix array can be fabricated.Type: ApplicationFiled: January 31, 2014Publication date: August 6, 2015Applicant: Sharp Laboratories of America, Inc.Inventors: Apostolos Voutsas, Themistokles Afentakis
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Patent number: 9063353Abstract: A plasmonic optical device is provided operating in near ultra violet (UV) and visible wavelengths of light. The optical device is made from a substrate and nanoparticles. The nanoparticles have a core with a negative real value relative permittivity of absolute value greater than 10 in a first range of wavelengths including near UV and visible wavelengths of light, and a shell with an imaginary relative permittivity of less than 5 in the first range of wavelengths. A dielectric overlies the substrate, and is embedded with the nanoparticles. If the substrate is reflective, a reflective optical filter is formed. If the substrate is transparent, the filter is transmissive. In one aspect, the dielectric is a tunable medium (e.g., liquid crystal) having an index of refraction responsive to an electric field. The tunable medium is interposed between a first electrode and a second electrode.Type: GrantFiled: December 13, 2012Date of Patent: June 23, 2015Assignee: Sharp Laboratories of America, Inc.Inventors: Akinori Hashimura, Douglas Tweet, Apostolos Voutsas
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Publication number: 20150029229Abstract: A scrollable display is provided with an adjustable screen size and an associated image scaling method. The display includes a case or housing, with an exit slot. The display also includes a flexible electronic screen having an input to accept electronic image signals, and a surface to display images. A screen extension mechanism is embedded in the case and connected to the flexible electronic screen interior edge. The screen extension mechanism is configured to permit the extension of the flexible electronic screen, through an exit slot, into a plurality of exposed widths. An image scaler has an input to accept a screen width measurement corresponding to an exposed width of the flexible electronic screen. The image scaler has an output to supply electronic image signals scaled to the screen width measurement, to form an image on an exposed section of the flexible electronic screen.Type: ApplicationFiled: July 27, 2013Publication date: January 29, 2015Applicant: Sharp Laboratories of America, Inc.Inventor: Apostolos Voutsas
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Publication number: 20070228471Abstract: A method is provided for concurrently forming MP-TFTs and P-TFTs. Generally, the method comprises: forming a P-TFT having source/drain (S/D) regions, an intervening channel region, and a gate, all in a first horizontal plane; and simultaneously forming a MP-TFT having a first gate in the first horizontal plane and at least one S/D region in a second horizontal plane, overlying the first horizontal plane. The vertical TFT (V-TFT) is an MP-TFT having vertical first gate sidewalls and a vertical channel region overlying a gate sidewall. The dual-gate TFT (DG-TFT) is an MP-TFT having a bottom gate, first and second S/D regions with top surfaces, an intervening channel region with a top surface, and a second, top gate with a bottom surface, all in a second horizontal plane, overlying the first horizontal plane.Type: ApplicationFiled: May 25, 2007Publication date: October 4, 2007Inventors: Paul Schuele, Apostolos Voutsas
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Publication number: 20070222493Abstract: A digital-to-time converter (DTC) is provided, made from a plurality of series-connected cells. Each cell has an input interface to accept a signal, a control interface to accept a digital command, a delayed signal path, a minimum delay signal path, and an output interface. The signal path is selected in response to the command. The time delay associated with the delayed signal path of each cell can be varied, so that the plurality of series-connected cells is able to provide a large range of delay combinations. For example, if there are n series-connected cells, then the jth series-connected cell, where j varies from 1 to n, conducts the signal through 2j MOS gates in the delayed signal path. Assuming a digital control word with n bit places, the jth series-connected cell accepts the jth bit place of the control word to select a delay path.Type: ApplicationFiled: May 23, 2006Publication date: September 27, 2007Inventors: Themistokles Afentakis, Apostolos Voutsas, Paul Schuele
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Publication number: 20070155137Abstract: A high-density plasma method is provided for forming a SiOXNY thin-film. The method provides a substrate and introduces a silicon (Si) precursor. A thin-film is deposited overlying the substrate, using a high density (HD) plasma-enhanced chemical vapor deposition (PECVD) process. As a result, a SiOXNY thin-film is formed, where (X+Y<2 and Y>0). The SiOXNY thin-film can be stoichiometric or non-stoichiometric. The SiOXNY thin-film can be graded, meaning the values of X and Y vary with the thickness of the SiOXNY thin-film. Further, the process enables the in-situ deposition of a SiOXNY thin-film multilayer structure, where the different layers may be stoichiometric, non-stoichiometric, graded, and combinations of the above-mentioned types of SiOXNY thin-films.Type: ApplicationFiled: January 26, 2007Publication date: July 5, 2007Inventors: Pooran Joshi, Apostolos Voutsas, John Hartzell
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Publication number: 20070107655Abstract: A mask with sub-resolution aperture features and a method for smoothing an annealed surface using a sub-resolution mask pattern are provided. The method comprises: supplying a laser beam having a first wavelength; supplying a mask with a first mask section having apertures with a first dimension and a second mask section with apertures having a second dimension, less than the first dimension; applying a laser beam having a first energy density to a substrate region; melting a substrate region in response to the first energy density; crystallizing the substrate region; applying a diffracted laser beam to the substrate region; and, in response to the diffracted laser beam, smoothing the substrate region surface. In some aspects of the method, applying a diffracted laser beam to the substrate area includes applying a diffracted laser beam having a second energy density, less than the first energy density, to the substrate region.Type: ApplicationFiled: January 13, 2007Publication date: May 17, 2007Inventors: Yasuhiro Mitani, Apostolos Voutsas, Mark Crowder
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Patent number: 7153730Abstract: A method is provided for crystallizing a silicon film in liquid crystal display (LCD) fabrication. The method comprises: forming an amorphous silicon film having a thickness in the range of 100 to 1000 Angstroms (?); irradiating the silicon film with a laser pulse having a pulse width of 50 nanoseconds (ns) or greater, as measured at the full-width-half-maximum (FWHM), using a beamlet width in the range of 3 to 20 microns; and, in response to irradiating the silicon film, laterally growing crystal grains. In one example, irradiating the silicon film may include irradiating with a pulse having a pulse width in the range between 30 and 300 ns FWHM, and an energy density in the range from 200 to 1300 millijoules per square centimeter (mJ/cm2).Type: GrantFiled: March 10, 2003Date of Patent: December 26, 2006Assignee: Sharp Laboratories of America, IncInventor: Apostolos Voutsas
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Publication number: 20060246637Abstract: A sidewall gate thin-film transistor (TFT) and associated fabrication method are provided. The method provides a substrate with a surface and forms a surface-normal feature. The surface-normal feature is normal with respect to the substrate surface, with a sidewall made from an electrical insulator. An active silicon (Si) layer is formed overlying the surface-normal feature, with a channel overlying the surface-normal feature sidewall. A gate insulator overlies the channel, and a sidewall gate overlies the gate insulator. More specifically, the gate insulator is formed from conformally depositing an electrical insulator layer overlying the active Si layer. The gate electrode layer is conformally deposited overlying the gate insulator layer and anisotropically etched, leaving a gate electrode sidewall adjacent to the gate insulator layer overlying the channel.Type: ApplicationFiled: June 30, 2006Publication date: November 2, 2006Inventors: Apostolos Voutsas, Paul Schuele
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Publication number: 20060211267Abstract: A method is provided for forming a silicon oxide (SiOx) thin-film with embedded nanocrystalline silicon (Si). The method deposits SiOx, where x is in the range of 1 to 2, overlying a substrate, using a high-density (HD) plasma-enhanced chemical vapor deposition (PECVD) process. As a result, the SiOx thin-film is embedded with nanocrystalline Si. The HD PECVD process may use an inductively coupled plasma (ICP) source, a substrate temperature of less than about 400° C., and an oxygen source gas with a silicon precursor. In one aspect, a hydrogen source gas and an inert gas are used, where the ratio of oxygen source gas to inert gas is in the range of about 0.02 to 5. The SiOx thin-film with embedded nanocrystalline Si typically has a refractive index in the range of about 1.6 to 2.2, with an extinction coefficient in the range of 0 to 0.5.Type: ApplicationFiled: May 4, 2006Publication date: September 21, 2006Inventors: Pooran Joshi, Tingkai Li, Yoshi Ono, Apostolos Voutsas, John Hartzell