Patents by Inventor Apratim Dhar

Apratim Dhar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250029892
    Abstract: Structures having a through-stack thermal sink for dual-sided devices are described. In an example, an integrated circuit structure includes a front side structure. The front side structure includes a device layer having a plurality of fin-based or nanowire-based transistors, and a plurality of metallization layers above the plurality of fin-based or nanowire-based transistors. A backside structure is below the plurality of fin-based or nanowire-based transistors. A carrier wafer or substrate is bonded to the front side structure. A thermal conductive via extends from a location at a bottom of or below the plurality of fin-based or nanowire-based transistors to a location on or into the carrier wafer or substrate.
    Type: Application
    Filed: July 18, 2023
    Publication date: January 23, 2025
    Inventors: Conor P. PULS, Giorgio MARIOTTINI, Brenden ARRUDA, Shawna M. LIFF, Lei JIANG, Samson ODUNUGA, Gerardo MONTANO, Hannes GREVE, Apratim DHAR, Aaron M. WHITE
  • Publication number: 20240363628
    Abstract: Gate-all-around integrated circuit structures having adjacent island structures are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A first vertical arrangement of horizontal nanowires is above a first fin protruding from the semiconductor substrate. A channel region of the first vertical arrangement of horizontal nanowires is electrically isolated from the fin. A second vertical arrangement of horizontal nanowires is above a second fin protruding from the semiconductor substrate. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. The semiconductor island is between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires.
    Type: Application
    Filed: July 9, 2024
    Publication date: October 31, 2024
    Inventors: Leonard P. GULER, William HSU, Biswajeet GUHA, Martin WEISS, Apratim DHAR, William T. BLANTON, John H. IRBY, IV, James F. BONDI, Michael K. HARPER, Charles H. WALLACE, Tahir GHANI, Benedict A. SAMUEL, Stefan DICKERT
  • Patent number: 12068314
    Abstract: Gate-all-around integrated circuit structures having adjacent island structures are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A first vertical arrangement of horizontal nanowires is above a first fin protruding from the semiconductor substrate. A channel region of the first vertical arrangement of horizontal nanowires is electrically isolated from the fin. A second vertical arrangement of horizontal nanowires is above a second fin protruding from the semiconductor substrate. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. The semiconductor island is between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: August 20, 2024
    Assignee: Intel Corporation
    Inventors: Leonard P. Guler, William Hsu, Biswajeet Guha, Martin Weiss, Apratim Dhar, William T. Blanton, John H. Irby, IV, James F. Bondi, Michael K. Harper, Charles H. Wallace, Tahir Ghani, Benedict A. Samuel, Stefan Dickert
  • Patent number: 11748869
    Abstract: Embodiments disclosed herein include a lithography reticle set and methods of using such reticle sets. In an embodiment, the set comprises a first reticle and a second reticle. In an embodiment, the first reticle comprises a first grating having a first pitch, and a second grating having a second pitch. In an embodiment, the second reticle comprises a third grating having a third pitch, wherein the third pitch is different than the first pitch, and a fourth grating having a fourth pitch, wherein the fourth pitch is different than the first pitch. In an embodiment the third grating overlaps the first grating and the fourth grating overlaps the second grating when two or more edges of the first reticle are aligned with two or more edges of the second reticle. In an embodiment the first reticle or the second reticle further comprises a pattern recognition feature.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: September 5, 2023
    Assignee: Intel Corporation
    Inventors: Martin Weiss, Apratim Dhar, Aaron M. White
  • Publication number: 20220093589
    Abstract: Gate-all-around integrated circuit structures having adjacent island structures are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A first vertical arrangement of horizontal nanowires is above a first fin protruding from the semiconductor substrate. A channel region of the first vertical arrangement of horizontal nanowires is electrically isolated from the fin. A second vertical arrangement of horizontal nanowires is above a second fin protruding from the semiconductor substrate. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. The semiconductor island is between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires.
    Type: Application
    Filed: September 18, 2020
    Publication date: March 24, 2022
    Inventors: Leonard P. GULER, William HSU, Biswajeet GUHA, Martin WEISS, Apratim DHAR, William T. BLANTON, John H. IRBY, IV, James F. BONDI, Michael K. HARPER, Charles H. WALLACE, Tahir GHANI, Benedict A. SAMUEL, Stefan DICKERT
  • Patent number: 8757871
    Abstract: An apparatus and methods for characterizing the response of a particle to a parameter that characterizes an environment of the particle. A change is induced in the parameter characterizing the environment of the particle, where the change is rapid on a timescale characterizing kinetic response of the particle. The response of the particle is then imaged at a plurality of instants over the course of a period of time shorter than the timescale characterizing the kinetic response of the particle. The response may be detected by measuring a temperature jump or by measuring correlation and anticorrelation between probe parameters across pixels. More particularly, the particle may be a molecule, such as a biomolecule, and the environment, more particularly, may be a biological cell. The parameter characterizing the environment of the particle may be a temperature, and change may be induced in the temperature by heating a volume that includes the particle, either conductively or radiatively.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: June 24, 2014
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Martin Gruebele, Simon Ebbinghaus, Apratim Dhar, J Douglas McDonald
  • Publication number: 20120039353
    Abstract: An apparatus and methods for characterizing the response of a particle to a parameter that characterizes an environment of the particle. A change is induced in the parameter characterizing the environment of the particle, where the change is rapid on a timescale characterizing kinetic response of the particle. The response of the particle is then imaged at a plurality of instants over the course of a period of time shorter than the timescale characterizing the kinetic response of the particle. The response may be detected by measuring a temperature jump or by measuring correlation and anticorrelation between probe parameters across pixels. More particularly, the particle may be a molecule, such as a biomolecule, and the environment, more particularly, may be a biological cell. The parameter characterizing the environment of the particle may be a temperature, and change may be induced in the temperature by heating a volume that includes the particle, either conductively or radiatively.
    Type: Application
    Filed: August 16, 2011
    Publication date: February 16, 2012
    Applicant: The Board of Trustees of the University of Illinois
    Inventors: Martin Gruebele, Simon Ebbinghaus, Apratim Dhar, J. Douglas McDonald