Patents by Inventor April Chen

April Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250085400
    Abstract: An optoelectronic assembly includes: (i) a substrate having a cavity, (ii) an optoelectronic device, which is disposed over the cavity and includes an array of multiple emitters configured to emit a predefined number of light beams in response to receiving one or more electrical signals, and (iii) an integrated circuit (IC), which is mounted within the cavity, between the substrate and the optoelectronic device, and is configured to drive the one or more electrical signals to the optoelectronic device.
    Type: Application
    Filed: September 11, 2024
    Publication date: March 13, 2025
    Inventors: Xiaoyin Zhu, Ali M. Khan, Andrea Manavella, Andrej Halabica, April D. Schriker, Austin Y. Seol, Bhavin J. Bijlani, Caihua Chen, Chin Han Lin, Cristiano L. Niclass, David Sicard, Eric D. Aspnes, Hazel A. McInnes, Henry M. Daghighian, Igor Raginski, Jiayang Cao, Jibum Cha, Jili Liu, Jose M. Infante Herrero, Julien Sarry, Karen A. Cabrera, Lorenzo Ferrari, Niv Gilboa, Noriaki Saika, Pietro R. Binetti, Pushkar Pandit, Reema Shalan, Scott T. Smith, Shifa Xu, Shingo Mandai, Shujun Tang, Sibi Sutty, Susan A. Thompson, Teimour T. Maleki, Thierry Oggier, Vikrant Dhamdhere, Yohai Zmora, Yuanlin Xie, Wee Keat Chong
  • Patent number: 6392425
    Abstract: A multi-chip packaging substrate having a non-sticking test structure consists of a plurality of non-sticking test spots formed in the periphery zone outside the chip-packaging zone of a multi-chip packaging substrate. Each of these non-sticking test spots is electrically connected to an adjacent one of a plurality of chip pads respectively in the chip packaging zone through a plurality of conductive traces while there are no electrical connections connected one another among the chip pads.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: May 21, 2002
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: April Chen, Chih-Chin Liao, Tzong-Dar Her
  • Patent number: 6291260
    Abstract: A crack-preventive substrate for fabricating a solder mask in a device site region includes a substrate, which has a top surface and a bottom surface, and a solder mask layer. The substrate is divided into a device site region and a periphery region. The solder mask layer, disposed on the top surface and bottom surface of the substrate, forms a bare area on the top surface and bottom surface of the substrate by exposing a portion of the substrate on the top surface and bottom surface of the substrate. And the bare areas divide the solder mask layer into a “device site region solder mask layer” and a “periphery region solder mask layer”. As a result, the crack lines generated on the solder mask layer at the perimeter of the substrate will not develop toward the solder mask in the device site region.
    Type: Grant
    Filed: January 13, 2000
    Date of Patent: September 18, 2001
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chien-Ping Huang, April Chen, Tzong-Dar Her