Patents by Inventor April Gurba
April Gurba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7560792Abstract: Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. A first dielectric layer (30) is formed on a semiconductor substrate (10). A first plasma nitridation process is performed on said first dielectric layer. The first dielectric layer (30) is removed in regions of the substrate and a second dielectric layer (50) is formed in these regions. A second plasma nitridation process is performed on the first dielectric layer and the second dielectric layer. MOS transistors (160, 170) are then fabricated using the dielectric layers (30, 50).Type: GrantFiled: January 24, 2007Date of Patent: July 14, 2009Assignee: Texas Instruments IncorporatedInventors: Rajesh Khamankar, Douglas T. Grider, Hiroaki Niimi, April Gurba, Toan Tran, James J. Chambers
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Patent number: 7402524Abstract: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region, wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer, and subjecting the exposed nitridated, high voltage dielectric to a high vacuum to remove the accelerant residue.Type: GrantFiled: December 2, 2005Date of Patent: July 22, 2008Assignee: Texas Instruments IncorporatedInventors: Brian K. Kirkpatrick, Rajesh Khamankar, Malcolm J. Bevan, April Gurba, Husam N. Alshareef, Clinton L. Montgomery, Mark H. Somervell
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Publication number: 20080076076Abstract: In one embodiment, a method of manufacturing an integrated circuit that comprises forming a circuit layer over a substrate, forming a resist layer on the circuit layer, and subjecting the resist layer to a rework process that includes exposing the resist layer to an organic wash. In another embodiment, the method of manufacturing an integrated circuit comprises forming a circuit layer over a substrate, forming a priming layer on the circuit layer, and subjecting the resist layer to the rework process. The reworking process includes exposing the substrate to a mild plasma ash to substantially remove portions of the resist layer but leave the priming layer.Type: ApplicationFiled: September 22, 2006Publication date: March 27, 2008Applicant: Texas Instruments IncorporatedInventors: Yaw Samuel Obeng, Yu-Tai Lee, Rajesh Khamankar, April Gurba, Brian Kirkpatrick, Ajith Varghese
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Patent number: 7339240Abstract: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer. The method further includes subjecting the exposed nitridated, high voltage dielectric to a plasma to remove the accelerant residue.Type: GrantFiled: January 31, 2006Date of Patent: March 4, 2008Assignee: Texas Instruments IncorporatedInventors: Brian K. Kirkpatrick, Rajesh Khamankar, Malcolm J. Bevan, April Gurba, Husam N. Alshareef, Clinton L. Montgomery, Mark H. Somervell
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Publication number: 20070117331Abstract: Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. A first dielectric layer (30) is formed on a semiconductor substrate (10). A first plasma nitridation process is performed on said first dielectric layer. The first dielectric layer (30) is removed in regions of the substrate and a second dielectric layer (50) is formed in these regions. A second plasma nitridation process is performed on the first dielectric layer and the second dielectric. MOS transistors (160, 170) are then fabricated using the dielectric layers (30, 50).Type: ApplicationFiled: January 24, 2007Publication date: May 24, 2007Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Rajesh Khamankar, Douglas Grider, Hiroaki Niimi, April Gurba, Toan Tran, James Chambers
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Patent number: 7183165Abstract: Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. A first dielectric layer (30) is formed on a semiconductor substrate (10). A first plasma nitridation process is performed on said first dielectric layer. The first dielectric layer (30) is removed in regions of the substrate and a second dielectric layer (50) is formed in these regions. A second plasma nitridation process is performed on the first dielectric layer and the second dielectric layer. MOS transistors (160, 170) are then fabricated using the dielectric layers (30, 50).Type: GrantFiled: November 6, 2003Date of Patent: February 27, 2007Assignee: Texas Instruments IncorporatedInventors: Rajesh Khamankar, Douglas T. Grider, Hiroaki Niimi, April Gurba, Toan Tran, James J. Chambers
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Publication number: 20060183337Abstract: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer. The method further includes subjecting the exposed nitridated, high voltage dielectric to a plasma to remove the accelerant residue.Type: ApplicationFiled: January 31, 2006Publication date: August 17, 2006Inventors: Brian Kirkpatrick, Rajesh Khamankar, Malcolm Bevan, April Gurba, Husam Alshareef, Clinton Montgomery, Mark Somervell
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Patent number: 7087440Abstract: The present invention provides, in one embodiment, a method method of monitoring a process for forming a nitridated oxide gate dielectric. A nitrided oxide dielectric layer is formed on a test substrate (110). The nitrided oxide dielectric layer is exposed to an etch process (120). A change in a property of the nitrided oxide dielectric layer is measured as a function of the etch process (130). Other embodiments advantageously incorporate the method into methods for making semiconductor devices and integrated circuits.Type: GrantFiled: May 23, 2003Date of Patent: August 8, 2006Assignee: Texas Instruments CorporationInventors: April Gurba, Husam Alshareef, Hiroaki Niimi
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Patent number: 7049242Abstract: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer. The method further includes subjecting the exposed nitridated, high voltage dielectric to a plasma to remove the accelerant residue.Type: GrantFiled: January 6, 2004Date of Patent: May 23, 2006Assignee: Texas Instruments IncorporatedInventors: Brian K. Kirkpatrick, Rajesh Khamankar, Malcolm J. Bevan, April Gurba, Husam N. Alshareef, Clinton L. Montgomery, Mark H. Somervell
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Publication number: 20060084229Abstract: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region, wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer, and subjecting the exposed nitridated, high voltage dielectric to a high vacuum to remove the accelerant residue.Type: ApplicationFiled: December 2, 2005Publication date: April 20, 2006Inventors: Brian Kirkpatrick, Rajesh Khamankar, Malcolm Bevan, April Gurba, Husam Alshareef, Clinton Montgomery, Mark Somervell
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Patent number: 7018925Abstract: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region, wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer, and subjecting the exposed nitridated, high voltage dielectric to a high vacuum to remove the accelerant residue.Type: GrantFiled: January 6, 2004Date of Patent: March 28, 2006Assignee: Texas Instruments IncorporatedInventors: Brian K. Kirkpatrick, Rajesh Khamankar, Malcolm J. Bevan, April Gurba, Husam N. Alshareef, Clinton L. Montgomery, Mark H. Somervell
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Publication number: 20040266113Abstract: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region, wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer, and subjecting the exposed nitridated, high voltage dielectric to a high vacuum to remove the accelerant residue.Type: ApplicationFiled: January 6, 2004Publication date: December 30, 2004Applicant: Texas Instruments IncorporatedInventors: Brian K. Kirkpatrick, Rajesh Khamankar, Malcolm J. Bevan, April Gurba, Husam N. Alshareef, Clinton L. Montgomery, Mark H. Somervell
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Publication number: 20040235203Abstract: The present invention provides, in one embodiment, a method method of monitoring a process for forming a nitridated oxide gate dielectric. A nitrided oxide dielectric layer is formed on a test substrate (110). The nitrided oxide dielectric layer is exposed to an etch process (120). A change in a property of the nitrided oxide dielectric layer is measured as a function of the etch process (130). Other embodiments advantageously incorporate the method into methods for making semiconductor devices and integrated circuits.Type: ApplicationFiled: May 23, 2003Publication date: November 25, 2004Applicant: Texas Instruments, IncorporatedInventors: April Gurba, Husam Alshareef, Hiroaki Niimi
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Publication number: 20040142570Abstract: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer. The method further includes subjecting the exposed nitridated, high voltage dielectric to a plasma to remove the accelerant residue.Type: ApplicationFiled: January 6, 2004Publication date: July 22, 2004Applicant: Texas Instruments IncorporatedInventors: Brian K. Kirkpatrick, Rajesh Khamankar, Malcolm J. Bevan, April Gurba, Husam N. Alshareef, Clinton L. Montgomery, Mark H. Somervell
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Publication number: 20040102010Abstract: Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. A first dielectric layer (30) is formed on a semiconductor substrate (10). A first plasma nitridation process is performed on said first dielectric layer. The first dielectric layer (30) is removed in regions of the substrate and a second dielectric layer (50) is formed in these regions. A second plasma nitridation process is performed on the first dielectric layer and the second dielectric layer. MOS transistors (160, 170) are then fabricated using the dielectric layers (30, 50).Type: ApplicationFiled: November 6, 2003Publication date: May 27, 2004Inventors: Rajesh Khamankar, Douglas T. Grider, Hiroaki Niimi, April Gurba, Toan Tran, James J. Chambers
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Publication number: 20030235973Abstract: A novel nickel self-aligned silicide (SALICIDE) process technology (80) adapted for CMOS devices (54) with physical gate lengths of sub-40 nm. The excess silicidation problem (52) due to edge effect is effectively solved by using a low-temperature, in-situ formed Ni-rich silicide, preferably formed in a temperature range of 260-310° C. With this new process, excess poly gate silicidation is prevented. Island diode leakage current and breakdown voltage are also improved.Type: ApplicationFiled: June 21, 2002Publication date: December 25, 2003Inventors: Jiong-Ping Lu, Donald S. Miles, Ching-Te Lin, Jin Zhao, April Gurba, Yuqing Xu