Abstract: Example aspects include techniques for query processing over deep neural network runtimes. These techniques include receiving a query including a query operator and a trainable user defined function (UDF). In addition, the techniques include determining a query representation based on the query, and determining, for performing the query in a neural network runtime, an initial neural network program based on the query representation, the initial neural network program including a differentiable operators corresponding to the query operator. and executing the neural network program in the neural network runtime over the neural network data structure to generate a query result. Further, the techniques include training the initial neural network program via the neural network runtime to determine a trained neural network program, and executing the trained neural network program in the neural network runtime to generate inference information.

Abstract: Various embodiments provide a content addressable memory (CAM) architecture that utilizes non-bit addressable memory, such as a single or dual port random access memory. The CAM includes a first non-bit addressable memory, a second non-bit addressable memory, a multiplexer, a write operation encoder, a read operation encoder, and a match signal generator. In contrast to bit addressable memories, non-bit addressable memories are widely available, have high performance frequency, and are area efficient as compared to bit addressable memories. Accordingly, the CAM architecture described herein has low costs and time to market, increased processing time, and improved area efficiency.

Abstract: Various embodiments provide a content addressable memory (CAM) architecture that utilizes non-bit addressable memory, such as a single or dual port random access memory. The CAM includes a first non-bit addressable memory, a second non-bit addressable memory, a multiplexer, a write operation encoder, a read operation encoder, and a match signal generator. In contrast to bit addressable memories, non-bit addressable memories are widely available, have high performance frequency, and are area efficient as compared to bit addressable memories. Accordingly, the CAM architecture described herein has low costs and time to market, increased processing time, and improved area efficiency.