Abstract: A method for determining an effect of via/contact pattern density in via/contact etch rate of a wafer includes determining a neutral etchant species number flux intersecting each via/contact mouth as a function of local layout characteristics and determining variations in the neutral etchant species flux number as a function of the via/contact pattern density in a wafer scale. The comparison of these number fluxes provides the capability to discriminate an underetched or an overetched via/contact from normal vias/contacts satisfying an etch tolerance criterion. Chip designers can modify the layout design to minimize via/contact failures. Chip manufacturers can modify the etching process to minimize via/contact failures.

Abstract: An automated method of designing large digital integrated circuits using a software program to partition the design into physically realizable blocks and then create the connections between blocks so as to maximize operating speed and routability while minimizing the area of the resulting integrated circuit. Timing and physical constraints are generated for each physically realizable block so that standard-cell place and route software can create each block independently as if it were a separate integrated circuit.

Abstract: An electronic computer aided design system provides for automated operation of a plurality of design tools to produce multiply design solutions to an initial circuit layout. Through the user entry of relative weights for: power, timing and area, different solutions to an initial layout can be generated exhibiting the requested balance of improvements over the original layout. A novel parts placement process is disclosed which prioritizes the reconfiguration of the initial design in a manner which assures that the multiple solutions will be generated which exhibit improved performance over the original layout in accordance with the priorities established by the user.

Abstract: A system is disclosed for compacting an initial electronic layout of cells within an initial layout boundary. The system includes forming paths extending from a bottom edge of the layout to a top edge. The paths intersect cells of the initial layout. The system determines which of the paths are critical paths. Critical cuts are then determined. A critical cut is a cut that severs critical paths. A set of cells associated with a critical cut are removed from the layout and replaced in order to reduce the initial layout boundary.

Abstract: An automated method of designing large digital integrated circuits using a software program to partition the design into physically realizable blocks then create the connections between blocks so as to maximize operating speed and routability while minimizing the area of the resulting integrated circuit. Timing and physical constraints are generated for each physically realizable block so that standard-cell place and route software can create each block independently as if it were a separate integrated circuit.

Abstract: An automated method of designing large digital integrated circuits using a software program to partition the design into physically realizable blocks and then create the connections between blocks so as to maximize operating speed and routability while minimizing the area of the resulting integrated circuit. Timing and physical constraints are generated for each physically realizable block so that standard-cell place and route software can create each block independently as if it were a separate integrated circuit.

Abstract: An automated routing tool for routing interconnections between circuit elements, standard cells and/or cell blocks of cell-based designs which incorporates the best features of both currently known gate array routing techniques with currently known cell-based routing techniques. The invention eliminates the disadvantages of permitting the detailed router to adjust the relative positions of the circuit elements, standard cells and/or cell blocks during the detailed routing process. The method employs a topology manager which iteratively compacts the circuit topology while at the same time optimizing the routing of the interconnections among the circuit elements, standard cells and/or cell blocks of the circuit design. The method employs bin-based global routing, which identifies expandable boundaries and which provides input to a compaction routine which expands or contracts the expandable areas in accordance with the result of the global routing process.