Abstract: The polishing apparatus is capable of changing a pH value of slurry to adjust polishing rate and polishing a work piece with high flatness. The polishing apparatus comprises: a pressure vessel; a polishing plate provided in the pressure vessel; a pressing plate pressing a work piece onto the polishing plate; a driving unit relatively moving the polishing plate with respect to the pressing plate so as to polish the work piece; a gas supplying source supplying an alkaline gas or an acid gas into the pressure vessel; a gas discharging section discharging the supplied gas from the pressure vessel; and a slurry supplying unit supplying slurry onto the polishing plate. A pH value of the slurry is adjusted by dissolving the alkaline gas or the acid gas in the slurry.

Abstract: Dressing is performed by spraying a cleaning liquid onto a polishing pad and after that abrasive slurry injected from a nozzle is supplied to the polishing pad. Provided is a method of conditioning a polishing pad for semiconductor wafer which is suitable for keeping the polishing performance of a polishing pad, provided with a polishing device for semiconductor wafer, in a stable condition for a long time.

Abstract: The polishing apparatus is capable of changing a pH value of slurry to adjust polishing rate and polishing a work piece with high flatness. The polishing apparatus comprises: a pressure vessel; a polishing plate provided in the pressure vessel; a pressing plate pressing a work piece onto the polishing plate; a driving unit relatively moving the polishing plate with respect to the pressing plate so as to polish the work piece; a gas supplying source supplying an alkaline gas or an acid gas into the pressure vessel; a gas discharging section discharging the supplied gas from the pressure vessel; and a slurry supplying unit supplying slurry onto the polishing plate. A pH value of the slurry is adjusted by dissolving the alkaline gas or the acid gas in the slurry.

Abstract: A CMOS device is provided having a high concentration of nitrogen atoms at the SiO.sub.2 /Si interface reducing hot carrier effects associated with operating shorter devices at voltage levels typically used with longer devices. In one embodiment, the process for providing the CMOS device resistant to hot carrier effects makes use of a sacrificial oxide layer through which the nitrogen atoms are implanted and is then removed. Following removal of the sacrificial oxide layer, a gate oxide is grown giving a CMOS device having high nitrogen concentration at the SiO.sub.2 /Si interface. In an alternate embodiment, nitrogen atoms are implanted through the final gate oxide using an implantation energy which does not damage the oxide layer.

Abstract: A process for filling an isolation trench with a dielectric is described. The deposition pressure of a gas from which a silicon dioxide dielectric is deposited in a trench is changed on a real-time basis during such deposition. Such pressure gradually increases from about 20 mTORR to 900 mTORR. The result is that particle generation during the initial stages of the deposition is maintained at a low rate, while the high pressure needed to provide deposition in a trench as it is filled is provided.

Abstract: Threshold optimization for SOI transistors is achieved through the formation of a layer of positive charge within the gate to correspond to the positive polarity formed in the substrate by ion implantation for threshold voltage control. A positive charge layer is formed by furnishing sulfur ions on the substrate before growth of an oxide to form a portion of the gate oxide. The sulfur will form a charge layer on the surface of the oxide, and an additional oxide is then deposited on the same to form the gate oxide as a sandwich with the positive charge layer in the same.

Abstract: Threshold optimization for SOI transistors is achieved through the formation of a layer of charge within the gate oxide, which layer has a polarity corresponding to that of the ion implantation for threshold voltage control. A negative charge layer is formed by furnishing trace amounts of aluminum on the substrate before growth of an oxide to form a portion of the gate oxide. The aluminum will form a charge layer on the surface of the oxide and an additional oxide is then deposited on the same to form the gate oxide as a sandwich with the charge layer in the same.

Abstract: N.sub.2 implantation is used to increase the etch rate of a sacrificial oxide (sometimes referred to as the first gate oxide) in integrated circuitry. This implantation allows etching selectivity by changing the relative etch rates of materials. In the specific implementation described, a field oxide is also provided and this implantation increases the etch rate of the sacrificial oxide relative to that of the field oxide. No heat treatment is applied to the implanted material prior to etching having the ability to repair the damage caused by the bombardment.

Abstract: A method of controlling gate oxide thickness in the fabrication of semiconductor devices wherein a sacrificial gate oxide layer is formed on a semiconductor substrate surface. Nitrogens ions are implanted into select locations of the substrate through the sacrificial gate oxide layer, and the substrate and the gate oxide layer are then thermally annealed. The sacrificial gate oxide layer is then removed and a gate oxide layer is then formed on the substrate layer wherein the portion of the gate oxide layer formed on the nitrogen ion implanted portion of the substrate is thinner than the portion of the gate oxide layer formed on the non-nitrogen ion implanted portion.

Abstract: An improved process for planarizing an isolation barrier in the fabrication of a semiconductor chip involves reducing the etch rate of the field oxide independently of the sacrificial oxide layer. The field oxide layer is implanted with nitrogen ions and then thermally annealed resulting in a hardened and densified field oxide. In subsequent operations, a sacrificial oxide layer is formed on the semiconductor top surface by thermal oxidation. Upon etching with HF, the etch rate of the hardened field oxide is significantly reduced relative to untreated field oxide. Thus, the exposed hardened field oxide is etched at about the same rate as the sacrificial oxide layer. In the example given, the etch rate of untreated densified TEOS field oxide in 10:1 HF is 6.90 .ANG./sec, while the etch rate of TEOS field oxide hardened according to the processes of this invention is 5.90 .ANG./sec. After planarization using the hardened field oxide, depressions in the isolation barrier are eliminated.

Abstract: A tube furnace used for high-temperature processing of semiconductor wafers or the like employs features to improve the gas flow. One feature is reducing, or essentially eliminating, regions of gas recirculation in the outer annular region inherently present in a horizontal hot-wall atmospheric oxidation reactor equipped with a tubular cantilever for holding semiconductor wafers. The annular region is effectively isolated from the rest of the reactor by a solid circular quartz ring or barrier formed on the inner wall of the furnace tube, acting as a physical barrier against gas penetration inside the outer annulus.

Abstract: A tube furnace used for high-temperature processing of semiconductor wafers or the like employs features to improve the gas flow. A primary feature of this invention is improving the plug flow characteristics of the furnace by preventing the undesirable elongation of the gas jet entering the reaction system through the injector nozzle. This elongated gas jet induces unwanted turbulence within the system and causes premature and incomplete mixing of reactant gases in the longitudinal direction. Improvement in plug flow characteristics is attained by use of a quartz baffle at the entrance region of the reactor located a distance from the gas inlet. The shape and location of the baffle are such that it acts as a physical barrier against the elongated gas jet and confines the turbulence in the initial fill chamber created by the entrance region of the reactor and the baffle.

Abstract: A tube furnace used for high-temperature processing of semiconductor wafers or the like employs a cone-like shape for the gas inlet or nozzle where the reactant or insert gas enters the furnace tube. This conical nozzle produces a gas flow of faster velocities, following the flow streamlines, and avoids or minimizes recirculating gas cells. The amount of gas used in purging a tube with this configuration is reduced, and the time needed for thorough purging is also reduced. Greater process control, and enhanced process reproducibility, are also possible because of the reduction in overlap of process steps permitted by the faster purging. This feature of faster purging can, in addition, reduce the infiltration of ambient air which occurs during any processing step.

Abstract: A furnace used for high-temperature processing of semiconductor wafers employs a scavenger arrangement for removing effluent reactant gases which provides radial symmetry of gas flow. A scavenger chamber surrounds one end of a cylindrical furnace, and draws exhaust gases outward by a pressure differential. The scavenger chamber has a cylindrical quartz liner having a number of openings therein, the openings being circumferentially spaced about the end of the furnace so that gas flow is uniform and symmetrical. Preferably, these openings are in a plurality of groups, spaced from one another.

Abstract: A tube furnace used for high-temperature processing of semiconductor wafers employs an annular manifold around the opening of the furnace tube where the wafer boats enter and exit, and this manifold or collar has a number of gas outlets to produce a radially-inwardly directed curtain of inert gas, such as nitrogen, to provide a physical barrier to prevent ambient gas from entering the furnace tube when the tubular cantilever is removed for loading and unloading operations. The manifold may be of unitary construction or may be constructed in two half-cylindrical parts, with separate gas inlets for each, so that the manifold may be removed to allow cleaning or replacement of the furnace tube. A symmetrical scavenger box surrounds this end of the furnace tube, outward of the annular manifold, so the inert gas introduced by the manifold and any ambient gas are scavenged in a radially symmetric manner.