Patents by Inventor Arant Agrawal

Arant Agrawal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Architecture incorporating configurable controller for reducing on chip power leakage
    Patent number: 8286012
    Abstract: The present invention provides a method and system for controlling leakage power consumption at a System on Chip (SoC) level during a normal run or a boot-up mode. The leakage power reduction is achieved by incorporating a central programmable controller in the SoC architecture and test structures of idle SoC peripherals to place them into an Absolute Minimum Power consumption state with respect to static and dynamic power.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: October 9, 2012
    Assignee: STMicroelectronics Pvt. Ltd.
    Inventors: Satinder Singh Malhi, Arant Agrawal
  • ARCHITECTURE INCORPORATING CONFIGURABLE CONTROLLER FOR REDUCING ON CHIP POWER LEAKAGE
    Publication number: 20110202782
    Abstract: The present invention provides a method and system for controlling leakage power consumption at a System on Chip (SoC) level during a normal run or a boot-up mode. The leakage power reduction is achieved by incorporating a central programmable controller in the SoC architecture and test structures of idle SoC peripherals to place them into an Absolute Minimum Power consumption state with respect to static and dynamic power.
    Type: Application
    Filed: April 28, 2011
    Publication date: August 18, 2011
    Applicant: STMicroelectronics Pvt Ltd.
    Inventors: Satinder Singh MALHI, Arant Agrawal
  • Architecture incorporating configurable controller for reducing on chip power leakage
    Patent number: 7953994
    Abstract: The present invention provides a method and system for controlling leakage power consumption at a System on Chip (SoC) level during a normal run or a boot-up mode. The leakage power reduction is achieved by incorporating a central programmable controller in the SoC architecture and test structures of idle SoC peripherals to place them into an Absolute Minimum Power consumption state with respect to static and dynamic power.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: May 31, 2011
    Assignee: STMicroelectronics Pvt. Ltd.
    Inventors: Satinder Singh Malhi, Arant Agrawal
  • ARCHITECTURE INCORPORATING CONFIGURABLE CONTROLLER FOR REDUCING ON CHIP POWER LEAKAGE
    Publication number: 20080313480
    Abstract: The present invention provides a method and system for controlling leakage power consumption at a System on Chip (SoC) level during a normal run or a boot-up mode. The leakage power reduction is achieved by incorporating a central programmable controller in the SoC architecture and test structures of idle SoC peripherals to place them into an Absolute Minimum Power consumption state with respect to static and dynamic power.
    Type: Application
    Filed: March 25, 2008
    Publication date: December 18, 2008
    Applicant: STMicroelectronics Pvt. Ltd.
    Inventors: Satinder Singh MALHI, Arant Agrawal