Abstract: In an example, a semiconductor device includes a region of semiconductor material, a first dielectric over the region of semiconductor material, a first gate conductor over a first portion of the first dielectric, and a second gate conductor over a second portion of the first dielectric and laterally spaced apart from the first gate conductor. A first conductor is coupled to the first gate conductor and a second conductor coupled to the second gate conductor and laterally separated from the first conductor by a first spacing. A second dielectric is within the first spacing. The first conductor and the second conductor are laterally capacitively coupled, the first gate conductor is vertically capacitively coupled to the region of semiconductor material, and the second gate conductor is vertically capacitively coupled to the region of semiconductor material.

Abstract: In an example, a semiconductor structure includes a region of semiconductor material of a first conductivity type and a first side. A doped region of a second conductivity type is within the region of semiconductor material at a first depth. A semiconductor device in a first portion of the region of semiconductor material and includes a first current carrying region of the second conductivity type and a second current carrying region. A PN diode is in a second portion of the region of semiconductor material and includes a cathode region and anode region. The cathode region is coupled to the first current carrying region, the anode region is coupled to the doped region, and the doped region is configured to electrically isolate the semiconductor device from region of semiconductor material below the doped region in response to a forward bias applied to the semiconductor.

Abstract: In one embodiment, a method of forming a semiconductor device may include forming a sense resistor to receive a high voltage signal and form a sense signal that is representative of the high voltage signal. An embodiment of the sense resistor may optionally be formed overlying a polysilicon resistor. The method may also have an embodiment that may include forming a plurality of capacitors in parallel to portions of the sense resistor wherein the plurality of capacitors are connected together in series.

Abstract: In one embodiment, a method of forming a semiconductor device may include forming a sense resistor to receive a high voltage signal and form a sense signal that is representative of the high voltage signal. An embodiment of the sense resistor may optionally be formed overlying a polysilicon resistor. The method may also have an embodiment that may include forming a plurality of capacitors in parallel to portions of the sense resistor wherein the plurality of capacitors are connected together in series.

Abstract: In an embodiment, a semiconductor device includes a resistor that overlies a doped region of the semiconductor device. The resistor is formed into a pattern of a polygon spiral. An embodiment of the pattern of the resistor includes sides and corners. The material of the sides has a low resistivity and the material of the corners has a higher resistivity.

Abstract: In an embodiment, a semiconductor device includes a resistor that overlies a doped region of the semiconductor device. The resistor is formed as an elongated element that is formed into a pattern of a spiral. An embodiment of the pattern of the resistor includes a plurality of revolutions from the starting point to an ending point. The resistor material has one of a separation distance between adjacent revolutions that increases with distance along a periphery of the resistor material or a width of the resistor material that increases with distance along the periphery of the resistor material.

Abstract: In an embodiment, a semiconductor device includes a resistor that overlies a doped region of the semiconductor device. The resistor is formed into a pattern of a polygon spiral. An embodiment of the pattern of the resistor includes sides and corners. The material of the sides has a low resistivity and the material of the corners has a higher resistivity.

Abstract: In a general aspect, an integrated circuit (IC) can include a low-voltage region including a low-side driver circuit configured to control a low-side switch of a power converter. The IC can also include a high-voltage region including a floating region of a first conductivity and a high-voltage sensing device disposed in the floating region. The high-voltage sensing device can include a junction-field effect transistor (JFET), and a voltage divider. The voltage divider can include a first terminal coupled to a drain of the JFET, a second terminal coupled to a gate of the JFET, and a sense terminal, the voltage divider being configured to a provide, on the sense terminal. The IC can further include a high-side driver circuit coupled with the sense terminal. The high-side driver circuit can be configured to control a high-side switch of the power converter based on the voltage on the sense terminal.

Abstract: In an embodiment, a semiconductor device includes a resistor that overlies a doped region of the semiconductor device. The resistor is formed into a pattern of a polygon spiral. An embodiment of the pattern of the resistor includes sides and corners. The material of the sides has a low resistivity and the material of the corners has a higher resistivity.

Abstract: In an embodiment, a semiconductor device includes a resistor that overlies a doped region of the semiconductor device. The resistor is formed as an elongated element that is formed into a pattern of a spiral. An embodiment of the pattern of the resistor includes a plurality of revolutions from the starting point to an ending point. The resistor material has one of a separation distance between adjacent revolutions that increases with distance along a periphery of the resistor material or a width of the resistor material that increases with distance along the periphery of the resistor material.

Abstract: The disclosed embodiments include an ESD robust transistor with a compound-SCR protection. The transistor may include a semiconductor substrate having a first conductivity type, a drain region coupled with the semiconductor substrate having a drain SCR component with a first drain region of the first conductivity type and a second drain region of the second conductivity type. The transistor may also include a source coupled with the semiconductor substrate, a channel region of the second conductivity type, and a gate coupled with the channel region having SCR components with a first gate region of the first conductivity type and a second gate region of the second conductivity type. The drain SCR components and the gate SCR components may create a low resistance discharge path along the channel region that activates in response to the ESD such that the ESD discharges through the transistor without causing damage to the transistor.

Abstract: The disclosed embodiments include an ESD robust transistor with a compound-SCR protection. The transistor may include a semiconductor substrate having a first conductivity type, a drain region coupled with the semiconductor substrate having a drain SCR component with a first drain region of the first conductivity type and a second drain region of the second conductivity type. The transistor may also include a source coupled with the semiconductor substrate, a channel region of the second conductivity type, and a gate coupled with the channel region having SCR components with a first gate region of the first conductivity type and a second gate region of the second conductivity type. The drain SCR components and the gate SCR components may create a low resistance discharge path along the channel region that activates in response to the ESD such that the ESD discharges through the transistor without causing damage to the transistor.