Patents by Inventor ARAVIND C. APPASWAMY

ARAVIND C. APPASWAMY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180033784
    Abstract: A silicon controlled rectifier (SCR) using separate bipolar transistors is disclosed. The separate bipolar SCR enables access to internal feedback terminals of the SCR, which may then may be used to adjust the gain of individual bipolar transistors. Further embodiments provide custom design latch up immune solutions. The latch up immunity is achieved by integrating an active Field Effect Transistor (FET) into the internal feedback node of the SCR. This provides access to ‘feedback’ node of the SCR allowing for latch-up free SCR design. The active FET times out in a short time period (e.g., microseconds) thus shutting off the SCR feedback mechanism making the SCR latch-up immune.
    Type: Application
    Filed: August 1, 2016
    Publication date: February 1, 2018
    Applicant: Texas Instruments Incorporated
    Inventors: ARAVIND C. APPASWAMY, FARZAN FARBIZ
  • Publication number: 20170098643
    Abstract: According to an embodiment, a bipolar transistor is disclosed for Electrostatic discharge (ESD) management in integrated circuits. The bipolar transistor enables vertical current flow in a bipolar transistor cell configured for ESD protection. The bipolar transistor includes a selectively embedded P-type floating buried layer (PBL). The floating P-region is added in a standard NPN cell. During an ESD event, the base of the bipolar transistor extends to the floating P-region with a very small amount of current. The PBL layer can provide more holes to support the current resulting in decreased holding voltage of the bipolar transistor. With the selective addition of floating P-region, the current scalability of the bipolar transistor at longer pulse widths can be significantly improved.
    Type: Application
    Filed: June 3, 2016
    Publication date: April 6, 2017
    Applicant: Texas Instruments Incorporated
    Inventors: YANG XIU, ARAVIND C. APPASWAMY, AKRAM SALMAN, MARIANO DISSEGNA
  • Publication number: 20160156176
    Abstract: An electrostatic discharge (ESD) protection circuit includes a substrate having a semiconductor surface that the ESD protection circuit formed thereon. A first ESD cell is stacked in series with at least a second ESD cell. An active shunt transistor is electrically in parallel with the first ESD cell or second ESD cell, where the active shunt includes a control node. A trigger circuit has a trigger input and a trigger output, wherein the trigger output is coupled to the control node.
    Type: Application
    Filed: December 2, 2014
    Publication date: June 2, 2016
    Inventors: JOHN ERIC KUNZ, JR., FARZAN FARBIZ, ARAVIND C. APPASWAMY, AKRAM A. SALMAN
  • Publication number: 20130264640
    Abstract: A method of forming a drain extended metal-oxide-semiconductor (MOS) transistor includes forming a gate structure including a gate electrode on a gate dielectric on a semiconductor surface portion of a substrate. The semiconductor surface portion has a first doping type. A source is formed on one side of the gate structure having a second doping type. A drain is formed including a highly doped portion on another side of the gate structure having the second doping type. A masking layer is formed on a first portion of a surface area of the highly doped drain portion. A second portion of the surface area of the highly doped drain portion does not have the masking layer. Selectively siliciding is used to form silicide on the second portion. The masking layer blocks siliciding on the first portion so that the first portion is silicide-free.
    Type: Application
    Filed: April 6, 2012
    Publication date: October 10, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: AKRAM A. SALMAN, FARZAN FARBIZ, ARAVIND C. APPASWAMY, JOHN ERIC KUNZ, JR., GIANLUCA BOSELLI