Patents by Inventor ARAVIND C. APPASWAMY

ARAVIND C. APPASWAMY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210091068
    Abstract: An electrostatic discharge (ESD) device with fast response to high transient currents. The ESD device includes a short-pulse discharge (SPD) path and a long-pulse discharge (LPD) path. The SPD path provides robust response to ESD events, and it triggers a self-bias configuration of the LPD path. Advantageously, the SPD path reduces the risk of ESD voltage overshoot by promptly discharging short-pulse currents, such as a charge device model (CDM) current, whereas the LPD path provides efficient discharge of long-pulse currents, such as a human body model (HBM) current. In one implementation, for example, the SPD path includes a MOS transistor, and the LPD includes a bipolar transistor having a base coupled to the source of the MOS transistor.
    Type: Application
    Filed: December 7, 2020
    Publication date: March 25, 2021
    Inventors: Aravind C. Appaswamy, James P. Di Sarro
  • Patent number: 10861844
    Abstract: An electrostatic discharge (ESD) device with fast response to high transient currents. The ESD device includes a short-pulse discharge (SPD) path and a long-pulse discharge (LPD) path. The SPD path provides robust response to ESD events, and it triggers a self-bias configuration of the LPD path. Advantageously, the SPD path reduces the risk of ESD voltage overshoot by promptly discharging short-pulse currents, such as a charge device model (CDM) current, whereas the LPD path provides efficient discharge of long-pulse currents, such as a human body model (HBM) current. In one implementation, for example, the SPD path includes a MOS transistor, and the LPD includes a bipolar transistor having a base coupled to the source of the MOS transistor.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: December 8, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aravind C. Appaswamy, James P. Di Sarro
  • Patent number: 10607984
    Abstract: According to an embodiment, a bipolar transistor is disclosed for Electrostatic discharge (ESD) management in integrated circuits. The bipolar transistor enables vertical current flow in a bipolar transistor cell configured for ESD protection. The bipolar transistor includes a selectively embedded P-type floating buried layer (PBL). The floating P-region is added in a standard NPN cell. During an ESD event, the base of the bipolar transistor extends to the floating P-region with a very small amount of current. The PBL layer can provide more holes to support the current resulting in decreased holding voltage of the bipolar transistor. With the selective addition of floating P-region, the current scalability of the bipolar transistor at longer pulse widths can be significantly improved.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: March 31, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yang Xiu, Aravind C. Appaswamy, Akram Salman, Mariano Dissegna
  • Publication number: 20200075584
    Abstract: An integrated circuit is fabricated on a semiconductor substrate. An insulated gate bipolar transistor (IGBT) is formed upon the semiconductor substrate in which the IGBT has an anode terminal, a cathode terminal, and a gate terminal, and a drift region. A diode is also formed on the semiconductor substrate and has an anode terminal and a cathode terminal, in which the anode of the diode is coupled to the anode terminal of the IGBT and the cathode of the diode is coupled to the drift region of the IGBT.
    Type: Application
    Filed: November 11, 2019
    Publication date: March 5, 2020
    Inventors: Aravind C. Appaswamy, James P. Di Sarro, Farzan Farbiz
  • Patent number: 10529708
    Abstract: An integrated circuit is fabricated on a semiconductor substrate. An insulated gate bipolar transistor (IGBT) is formed upon the semiconductor substrate in which the IGBT has an anode terminal, a cathode terminal, and a gate terminal, and a drift region. A diode is also formed on the semiconductor substrate and has an anode terminal and a cathode terminal, in which the anode of the diode is coupled to the anode terminal of the IGBT and the cathode of the diode is coupled to the drift region of the IGBT.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: January 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aravind C Appaswamy, James P. Di Sarro, Farzan Farbiz
  • Patent number: 10396199
    Abstract: A semiconductor device includes a body and a transistor fabricated into the body. Isolation material at least partially encases the body. Biasing is coupled to the isolation material, wherein the biasing is for changing the electric potential of the isolation material in response to an electrostatic discharge event.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: August 27, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aravind C. Appaswamy, Akram A. Salman, Farzan Farbiz, Gianluca Boselli
  • Patent number: 10381342
    Abstract: According to an embodiment, a bipolar transistor is disclosed for Electrostatic discharge (ESD) management in integrated circuits. The bipolar transistor enables vertical current flow in a bipolar transistor cell configured for ESD protection. The bipolar transistor includes a selectively embedded P-type floating buried layer (PBL). The floating P-region is added in a standard NPN cell. During an ESD event, the base of the bipolar transistor extends to the floating P-region with a very small amount of current. The PBL layer can provide more holes to support the current resulting in decreased holding voltage of the bipolar transistor. With the selective addition of floating P-region, the current scalability of the bipolar transistor at longer pulse widths can be significantly improved.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: August 13, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yang Xiu, Aravind C Appaswamy, Akram Salman, Mariano Dissegna
  • Publication number: 20190043854
    Abstract: An electrostatic discharge (ESD) device with fast response to high transient currents. The ESD device includes a short-pulse discharge (SPD) path and a long-pulse discharge (LPD) path. The SPD path provides robust response to ESD events, and it triggers a self-bias configuration of the LPD path. Advantageously, the SPD path reduces the risk of ESD voltage overshoot by promptly discharging short-pulse currents, such as a charge device model (CDM) current, whereas the LPD path provides efficient discharge of long-pulse currents, such as a human body model (HBM) current. In one implementation, for example, the SPD path includes a MOS transistor, and the LPD includes a bipolar transistor having a base coupled to the source of the MOS transistor.
    Type: Application
    Filed: August 7, 2017
    Publication date: February 7, 2019
    Inventors: Aravind C. Appaswamy, James P. Di Sarro
  • Patent number: 10134721
    Abstract: A silicon controlled rectifier (SCR) using separate bipolar transistors is disclosed. The separate bipolar SCR enables access to internal feedback terminals of the SCR, which may then may be used to adjust the gain of individual bipolar transistors. Further embodiments provide custom design latch up immune solutions. The latch up immunity is achieved by integrating an active Field Effect Transistor (FET) into the internal feedback node of the SCR. This provides access to ‘feedback’ node of the SCR allowing for latch-up free SCR design. The active FET times out in a short time period (e.g., microseconds) thus shutting off the SCR feedback mechanism making the SCR latch-up immune.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: November 20, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aravind C Appaswamy, Farzan Farbiz
  • Patent number: 10026712
    Abstract: An electrostatic discharge (ESD) protection circuit includes a substrate having a semiconductor surface that the ESD protection circuit formed thereon. A first ESD cell is stacked in series with at least a second ESD cell. An active shunt transistor is electrically in parallel with the first ESD cell or second ESD cell, where the active shunt includes a control node. A trigger circuit has a trigger input and a trigger output, wherein the trigger output is coupled to the control node.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: July 17, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: John Eric Kunz, Jr., Farzan Farbiz, Aravind C. Appaswamy, Akram A. Salman
  • Publication number: 20180182755
    Abstract: An integrated circuit is fabricated on a semiconductor substrate. An insulated gate bipolar transistor (IGBT) is formed upon the semiconductor substrate in which the IGBT has an anode terminal, a cathode terminal, and a gate terminal, and a drift region. A diode is also formed on the s5emiconductor substrate and has an anode terminal and a cathode terminal, in which the anode of the diode is coupled to the anode terminal of the IGBT and the cathode of the diode is coupled to the drift region of the IGBT.
    Type: Application
    Filed: January 15, 2018
    Publication date: June 28, 2018
    Inventors: Aravind C Appaswamy, James P. Di Sarro, Farzan Farbiz
  • Patent number: 9905558
    Abstract: An integrated circuit is fabricated on a semiconductor substrate. An insulated gate bipolar transistor (IGBT) is formed upon the semiconductor substrate in which the IGBT has an anode terminal, a cathode terminal, and a gate terminal, and a drift region. A diode is also formed on the semiconductor substrate and has an anode terminal and a cathode terminal, in which the anode of the diode is coupled to the anode terminal of the IGBT and the cathode of the diode is coupled to the drift region of the IGBT.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: February 27, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aravind C Appaswamy, James P. Di Sarro, Farzan Farbiz
  • Publication number: 20180033784
    Abstract: A silicon controlled rectifier (SCR) using separate bipolar transistors is disclosed. The separate bipolar SCR enables access to internal feedback terminals of the SCR, which may then may be used to adjust the gain of individual bipolar transistors. Further embodiments provide custom design latch up immune solutions. The latch up immunity is achieved by integrating an active Field Effect Transistor (FET) into the internal feedback node of the SCR. This provides access to ‘feedback’ node of the SCR allowing for latch-up free SCR design. The active FET times out in a short time period (e.g., microseconds) thus shutting off the SCR feedback mechanism making the SCR latch-up immune.
    Type: Application
    Filed: August 1, 2016
    Publication date: February 1, 2018
    Applicant: Texas Instruments Incorporated
    Inventors: ARAVIND C. APPASWAMY, FARZAN FARBIZ
  • Patent number: 9881913
    Abstract: A high-voltage bipolar semiconductor controlled rectifier (SCR) includes an emitter region having a first polarity and overlying a base region having a second polarity different from the first polarity; a collector region having the first polarity and lying under the base region; an anode region having the second polarity; a first sinker region having the first polarity and contacting the collector region, wherein the anode region is between the first sinker region and the base region; and a second sinker region having the first polarity and contacting the collector region, the second sinker region lying between the anode region and the base region, wherein an extension of the anode region extends under a portion of the second sinker region.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: January 30, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aravind C. Appaswamy, Stanley Phillips
  • Patent number: 9818868
    Abstract: A drain extended metal oxide semiconductor (MOS) includes a substrate having a semiconductor. A gate is located on the semiconductor, a source is located on the semiconductor and on one side of the gate, and a drain is located on the semiconductor and on another side of said gate. The MOS includes least one first finger having a first finger drain component located adjacent the drain, the first finger drain component has a silicide layer. At least one second finger has a second finger drain component located adjacent the drain, the second finger drain component has less silicide than the first finger drain component.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: November 14, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aravind C. Appaswamy, Akram A. Salman, Farzan Farbiz
  • Publication number: 20170288058
    Abstract: A semiconductor device includes a body and a transistor fabricated into the body. Isolation material at least partially encases the body. Biasing is coupled to the isolation material, wherein the biasing is for changing the electric potential of the isolation material in response to an electrostatic discharge event.
    Type: Application
    Filed: June 16, 2017
    Publication date: October 5, 2017
    Inventors: Aravind C. Appaswamy, Akram A. Salman, Farzan Farbiz, Gianluca Boselli
  • Publication number: 20170287896
    Abstract: A high-voltage bipolar semiconductor controlled rectifier (SCR) includes an emitter region having a first polarity and overlying a base region having a second polarity different from the first polarity; a collector region having the first polarity and lying under the base region; an anode region having the second polarity; a first sinker region having the first polarity and contacting the collector region, wherein the anode region is between the first sinker region and the base region; and a second sinker region having the first polarity and contacting the collector region, the second sinker region lying between the anode region and the base region, wherein an extension of the anode region extends under a portion of the second sinker region.
    Type: Application
    Filed: March 20, 2017
    Publication date: October 5, 2017
    Inventors: Aravind C. Appaswamy, Stanley Phillips
  • Patent number: 9711643
    Abstract: A semiconductor device includes a body and a transistor fabricated into the body. Isolation material at least partially encases the body. Biasing is coupled to the isolation material, wherein the biasing is for changing the electric potential of the isolation material in response to an electrostatic discharge event.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: July 18, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aravind C. Appaswamy, Akram A. Salman, Farzan Farbiz, Gianluca Boselli
  • Patent number: 9633993
    Abstract: A high-voltage bipolar semiconductor controlled rectifier (SCR) includes an emitter region having a first polarity and overlying a base region having a second polarity different from the first polarity; a collector region having the first polarity and lying under the base region; an anode region having the second polarity; a first sinker region having the first polarity and contacting the collector region, wherein the anode region is between the first sinker region and the base region; and a second sinker region having the first polarity and contacting the collector region, the second sinker region lying between the anode region and the base region, wherein an extension of the anode region extends under a portion of the second sinker region.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: April 25, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aravind C Appaswamy, Stanley Phillips
  • Patent number: 9633990
    Abstract: An integrated circuit and method with a bidirectional ESD transistor. A base diffusion separates an emitter diffusion and a collector diffusion. Silicide is blocked from the base diffusion, the emitter-base junction, the collector-base junction, and from equal portions of the emitter diffusion and the collector diffusions.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: April 25, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Akram A. Salman, Farzan Farbiz, Aravind C. Appaswamy, Ann Margaret Concannon