Patents by Inventor Aravind Chennimalai Appaswamy

Aravind Chennimalai Appaswamy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240030218
    Abstract: An SCR with a first semiconductor region and plural concentric semiconductor regions, each surrounding the first semiconductor region. The SCR also includes, surrounded by at least one concentric semiconductor region in the plurality of concentric semiconductor regions, an electrically non-contacted region of a semiconductor type and positioned to modulate a snapback voltage of the silicon controlled rectifier and an electrically-contacted region of the semiconductor type and positioned to provide a diodic response between the at least one concentric semiconductor region in the plurality of concentric semiconductor regions and the electrically-contacted region.
    Type: Application
    Filed: September 28, 2023
    Publication date: January 25, 2024
    Inventor: Aravind Chennimalai Appaswamy
  • Patent number: 11817455
    Abstract: An SCR with a first semiconductor region and plural concentric semiconductor regions, each surrounding the first semiconductor region. The SCR also includes, surrounded by at least one concentric semiconductor region in the plurality of concentric semiconductor regions, an electrically non-contacted region of a semiconductor type and positioned to modulate a snapback voltage of the silicon controlled rectifier and an electrically-contacted region of the semiconductor type and positioned to provide a diodic response between the at least one concentric semiconductor region in the plurality of concentric semiconductor regions and the electrically-contacted region.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: November 14, 2023
    Assignee: Texas Instruments Incorporated
    Inventor: Aravind Chennimalai Appaswamy
  • Publication number: 20220223580
    Abstract: An electrostatic discharge protection system with a node adapted to receive a signal and threshold detecting circuitry coupled to the node. The system includes an IGBT having an IGBT gate coupled to an output of the threshold detecting circuitry, a resistor coupled between an IGBT emitter of the IGBT and a low reference potential node, and a BJT having a BJT base coupled to the IGBT emitter.
    Type: Application
    Filed: May 16, 2021
    Publication date: July 14, 2022
    Inventors: James Paul DiSarro, Aravind Chennimalai Appaswamy, Zaichen Chen
  • Publication number: 20220223584
    Abstract: An SCR with a first semiconductor region and plural concentric semiconductor regions, each surrounding the first semiconductor region. The SCR also includes, surrounded by at least one concentric semiconductor region in the plurality of concentric semiconductor regions, an electrically non-contacted region of a semiconductor type and positioned to modulate a snapback voltage of the silicon controlled rectifier and an electrically-contacted region of the semiconductor type and positioned to provide a diodic response between the at least one concentric semiconductor region in the plurality of concentric semiconductor regions and the electrically-contacted region.
    Type: Application
    Filed: June 15, 2021
    Publication date: July 14, 2022
    Inventor: Aravind Chennimalai Appaswamy
  • Publication number: 20220223683
    Abstract: A microelectronic device includes an integrated guard structure diode on the substrate. The integrated guard structure diode includes a first terminal of the diode, a second terminal of the diode, and a guard structure. The guard structure is between the first terminal of the diode and the second terminal of the diode. The first terminal of the diode and guard structure are electrically connected to each other. An optional switching element may provide selective electrical connection between the first terminal of the diode and the guard structure. Adding a guard structure electrically connected first terminal of the diode, with the guard structure between the first terminal of the diode and the second terminal of the diode provides higher break down voltage than a diode without a guard structure.
    Type: Application
    Filed: November 29, 2021
    Publication date: July 14, 2022
    Inventor: Aravind Chennimalai Appaswamy
  • Patent number: 10749336
    Abstract: Disclosed examples include an ESD protection circuit, including a transistor operative according to a control voltage signal at a control node to selectively conduct current from a protected node to a reference node during an ESD event, as well as a resistor connected between the control node and the reference node, a capacitor connected between the control node and an internal node, and a diode with an anode connected to the protected node and a cathode connected to the internal node to allow charging current to flow from the protected node to charge the capacitor and to provide a high impedance to the internal node to prevent or mitigate flow of leakage current from the internal node to the protected node to raise a trigger voltage of the protection circuit during normal operation.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: August 18, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Krishna Praveen Mysore Rajagopal, Ann Margaret Concannon, Vishwanath Joshi, Aravind Chennimalai Appaswamy, Mariano Dissegna
  • Patent number: 10249610
    Abstract: In some examples, an electrostatic discharge (ESD) device comprises an insulated-gate bipolar transistor (IGBT) comprising a source terminal, an anode terminal, a gate terminal, and a body terminal; and at least one reverse bias device comprising a first terminal and a second terminal, wherein the first terminal couples to the source terminal and the second terminal couples to the body terminal.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: April 2, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aravind Chennimalai Appaswamy, James P. Di Sarro, Krishna Praveen Mysore Rajagopal, Akram A. Salman, Muhammad Yusuf Ali
  • Publication number: 20180152019
    Abstract: Disclosed examples include an ESD protection circuit, including a transistor operative according to a control voltage signal at a control node to selectively conduct current from a protected node to a reference node during an ESD event, as well as a resistor connected between the control node and the reference node, a capacitor connected between the control node and an internal node, and a diode with an anode connected to the protected node and a cathode connected to the internal node to allow charging current to flow from the protected node to charge the capacitor and to provide a high impedance to the internal node to prevent or mitigate flow of leakage current from the internal node to the protected node to raise a trigger voltage of the protection circuit during normal operation.
    Type: Application
    Filed: November 28, 2016
    Publication date: May 31, 2018
    Applicant: Texas Instruments Incorporated
    Inventors: Krishna Praveen Mysore Rajagopal, Ann Margaret Concannon, Vishwanath Joshi, Aravind Chennimalai Appaswamy, Mariano Dissegna