Patents by Inventor Aravind Chennimalai Appaswamy

Aravind Chennimalai Appaswamy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10749336
    Abstract: Disclosed examples include an ESD protection circuit, including a transistor operative according to a control voltage signal at a control node to selectively conduct current from a protected node to a reference node during an ESD event, as well as a resistor connected between the control node and the reference node, a capacitor connected between the control node and an internal node, and a diode with an anode connected to the protected node and a cathode connected to the internal node to allow charging current to flow from the protected node to charge the capacitor and to provide a high impedance to the internal node to prevent or mitigate flow of leakage current from the internal node to the protected node to raise a trigger voltage of the protection circuit during normal operation.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: August 18, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Krishna Praveen Mysore Rajagopal, Ann Margaret Concannon, Vishwanath Joshi, Aravind Chennimalai Appaswamy, Mariano Dissegna
  • Patent number: 10249610
    Abstract: In some examples, an electrostatic discharge (ESD) device comprises an insulated-gate bipolar transistor (IGBT) comprising a source terminal, an anode terminal, a gate terminal, and a body terminal; and at least one reverse bias device comprising a first terminal and a second terminal, wherein the first terminal couples to the source terminal and the second terminal couples to the body terminal.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: April 2, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aravind Chennimalai Appaswamy, James P. Di Sarro, Krishna Praveen Mysore Rajagopal, Akram A. Salman, Muhammad Yusuf Ali
  • Publication number: 20180152019
    Abstract: Disclosed examples include an ESD protection circuit, including a transistor operative according to a control voltage signal at a control node to selectively conduct current from a protected node to a reference node during an ESD event, as well as a resistor connected between the control node and the reference node, a capacitor connected between the control node and an internal node, and a diode with an anode connected to the protected node and a cathode connected to the internal node to allow charging current to flow from the protected node to charge the capacitor and to provide a high impedance to the internal node to prevent or mitigate flow of leakage current from the internal node to the protected node to raise a trigger voltage of the protection circuit during normal operation.
    Type: Application
    Filed: November 28, 2016
    Publication date: May 31, 2018
    Applicant: Texas Instruments Incorporated
    Inventors: Krishna Praveen Mysore Rajagopal, Ann Margaret Concannon, Vishwanath Joshi, Aravind Chennimalai Appaswamy, Mariano Dissegna