Abstract: Methods and apparatuses are described for provisioning and managing data orchestration platforms in a cloud computing environment. A server provisions in a first region a first data orchestration platform comprising (i) a first data transformation instance, (ii) first endpoints, and (iii) a first data integration instance. The server provisions in a second region a second data orchestration platform comprising (i) a second data transformation instance, (ii) second endpoints, and (iii) a second data integration instance. The server integrates the first data integration instance and the second data integration instance with an identity authentication service. The server monitors operational status of the first orchestration platform and the second orchestration platform using a monitoring service. The server refreshes virtual computing resources in each of the first orchestration platform and the second orchestration platform using a rehydration service.

Abstract: A method for adapting a continuous time equalizer (CTE) includes determining a gain of a discrete time equalizer (DTE) and determining whether the gain has increased or decreased by more than the threshold amount. Responsive to determining that the gain has increased or decreased by more than the threshold amount, the method includes sequentially configuring the CTE for multiple CTE settings such that gain of the CTE is caused to increase or decrease in a same direction with the change in gain of the DTE. The method also includes determining a separate figure of merit (FOM) for each of the multiple CTE settings and selecting a new CTE setting from the multiple CTE settings based on the FOM for each of the multiple CTE settings.

Abstract: A signal transmission system includes an equalization filter configured to filter an input signal based at least in part on a feedback signal, a slicer configured to generate data based on the filtered input signal at a plurality of different phases, a synchronizer configured to compute a phase delay between the input signal at each of the different phases and the data, and a pattern generator configured to generate the feedback signal at a phase adjusted by the phase delay.

Abstract: Methods and apparatuses are described for provisioning and managing data orchestration platforms in a cloud computing environment. A server provisions in a first region a first data orchestration platform comprising (i) a first data transformation instance, (ii) first endpoints, and (iii) a first data integration instance. The server provisions in a second region a second data orchestration platform comprising (i) a second data transformation instance, (ii) second endpoints, and (iii) a second data integration instance. The server integrates the first data integration instance and the second data integration instance with an identity authentication service. The server monitors operational status of the first orchestration platform and the second orchestration platform using a monitoring service. The server refreshes virtual computing resources in each of the first orchestration platform and the second orchestration platform using a rehydration service.

Abstract: A signal transmission system includes an equalization filter configured to filter an input signal based at least in part on a feedback signal, a slicer configured to generate data based on the filtered input signal at a plurality of different phases, a synchronizer configured to compute a phase delay between the input signal at each of the different phases and the data, and a pattern generator configured to generate the feedback signal at a phase adjusted by the phase delay.

Abstract: A receiver circuit comprising an equalizer and a method of correcting offset in the equalizer. In an example, the equalizer includes a plurality of delay stages for sampling and storing a sequence input samples, and a plurality of coefficient gain stages, each coupled to a corresponding delay stage to apply a gain corresponding to a coefficient value. The outputs of the coefficient gain stages are summed to produce a weighted sum for quantization by a slicer. Offset correction circuitry is provided, including memory storing a look-up table (LUT) for each coefficient gain stage, each storing offset correction values corresponding to the available coefficient values for the coefficient gain stage. Addressing circuitry retrieves the offset correction values for the coefficient values currently selected for each gain stage, and applies an offset correction corresponding to the sum of the retrieved offset correction values.

Abstract: A system for programming an eFuse array in an integrated circuit (IC) includes an eFuse data file which has a first plurality of bits. The system includes a data compression module which has an input coupled to receive the eFuse data file. The data compression module reduces the size of the eFuse data file and provides a compressed data file. The compressed data file has fewer bits than the eFuse data file. The system includes an eFuse controller which has an input coupled to receive the compressed data file. The eFuse controller programs the eFuse array to permanently store the compressed data file in the eFuse array.

Abstract: A receiver circuit comprising an equalizer and a method of correcting offset in the equalizer. In an example, the equalizer includes a plurality of delay stages for sampling and storing a sequence input samples, and a plurality of coefficient gain stages, each coupled to a corresponding delay stage to apply a gain corresponding to a coefficient value. The outputs of the coefficient gain stages are summed to produce a weighted sum for quantization by a slicer. Offset correction circuitry is provided, including memory storing a look-up table (LUT) for each coefficient gain stage, each storing offset correction values corresponding to the available coefficient values for the coefficient gain stage. Addressing circuitry retrieves the offset correction values for the coefficient values currently selected for each gain stage, and applies an offset correction corresponding to the sum of the retrieved offset correction values.

Abstract: A circuit includes: a parallel data interface; and transition control circuitry coupled to the parallel data interface. The transition control circuitry is configured to: receive an input bit stream sample; determine a bit transformation pattern for the input bit stream sample in accordance with a target criteria; and generate an output bit stream symbol from the input bit stream sample and the bit transformation pattern, wherein the output bit stream symbol has more bits than the input bit stream sample.

Abstract: Adaptive equalizer circuitry including both a continuous time equalizer (CTE) and a discrete time equalizer (DTE) and a method of jointly adapting the CTE and DTE in lane adaptation. Jointly adaptation of the CTE and DTE is performed by adapting the DTE at each of a plurality of filter characteristic settings of the CTE and determining a figure of merit for signals filtered by the CTE and DTE at that condition. Adaptation of the DTE may be performed by dynamically adjusting a convergence coefficient based on a history of error gradients. After a figure of merit is determined for each of the plurality of CTE filter characteristics, a CTE filter characteristic setting is then selected based on those figure of merit values, for example at a CTE setting near a midpoint of an acceptable region of figure of merit values.

Abstract: A one-time write, read-only memory for storing trimming parameters includes an address pointer table, a fixed packet portion, and a flexible packet portion. The fixed packet portion includes one or more fixed packets, each fixed packet including trimming parameters for a component identified for trimming during a design phase. The flexible packet portion includes one or more flexible packets of different types. Each flexible packet includes trimming parameters for a component identified for trimming after the design phase. One packet type includes a length section and a number of fields equal to a value stored in the length section. Each field includes an address, a trimming parameter, and a mask. Another packet type includes trimming parameters associated with operands in operating instructions for a microcontroller, where the operands include an address and a mask.

Abstract: A clock data recovery circuit includes a phase detector (PD) having a data input, a second input, and an output. The circuit also includes a filter, first and second charge pumps, a voltage-controlled oscillator (VCO), and a frequency detector (FD). The first charge pump couples between the output of the PD and the filter. The VCO has first and second inputs and an output. The first input of the VCO couples to the filter, and the VCO output couple to the second input of the PD. The FD has a data input, a second input, and first and second outputs. The FD second output couples to the second input of the VCO. The FD data input couples to the data input of the phase detector, and the FD second input couples to the output of the VCO. The second charge pump couples between the FD first output and the filter.

Abstract: A one-time write, read-only memory for storing trimming parameters includes an address pointer table, a fixed packet portion, and a flexible packet portion. The fixed packet portion includes one or more fixed packets, each fixed packet including trimming parameters for a component identified for trimming during a design phase. The flexible packet portion includes one or more flexible packets of different types. Each flexible packet includes trimming parameters for a component identified for trimming after the design phase. One packet type includes a length section and a number of fields equal to a value stored in the length section. Each field includes an address, a trimming parameter, and a mask. Another packet type includes trimming parameters associated with operands in operating instructions for a microcontroller, where the operands include an address and a mask.

Abstract: A one-time write, read-only memory for storing trimming parameters includes an address pointer table, a fixed packet portion, and a flexible packet portion. The fixed packet portion includes one or more fixed packets, each fixed packet including trimming parameters for a component identified for trimming during a design phase. The flexible packet portion includes one or more flexible packets of different types. Each flexible packet includes trimming parameters for a component identified for trimming after the design phase. One packet type includes a length section and a number of fields equal to a value stored in the length section. Each field includes an address, a trimming parameter, and a mask. Another packet type includes trimming parameters associated with operands in operating instructions for a microcontroller, where the operands include an address and a mask.

Abstract: A one-time write, read-only memory for storing trimming parameters includes an address pointer table, a fixed packet portion, and a flexible packet portion. The fixed packet portion includes one or more fixed packets, each fixed packet including trimming parameters for a component identified for trimming during a design phase. The flexible packet portion includes one or more flexible packets of different types. Each flexible packet includes trimming parameters for a component identified for trimming after the design phase. One packet type includes a length section and a number of fields equal to a value stored in the length section. Each field includes an address, a trimming parameter, and a mask. Another packet type includes trimming parameters associated with operands in operating instructions for a microcontroller, where the operands include an address and a mask.

Abstract: A single-hop relay cellular system 300 and a multi-hop relay cellular system 400 including frequency links (102A-F), a backhaul link 104, an access link 106, and a relay base station 108 are provided. The relay base station 108 is configured to interchange a frequency of operation between a first frequency carrier 114A and a second frequency carrier 114B for uplink and downlink transmission. Each node in the single-hop relay cellular system 300 and the multi-hop relay cellular system 400 is enabled to transmit and receive on frequency carriers through static or dynamic control.

Abstract: A method for frequency domain to time domain conversion includes receiving a set of frequency-domain samples. Based on the set of frequency-domain samples, a first sample subset comprising a predetermined fraction of the number of samples of the set of frequency-domain samples and a second sample subset comprising the predetermined fraction of the number of samples of the set of frequency-domain samples are generated. A linear phase rotation is applied to the first sample subset and the second sample subset to produce a phase rotated first sample subset and a phase rotated second sample subset. The phase rotated first sample set is post-processed to generate a first set of time-domain samples. The phase rotated second sample set is post-processed to generate a second set of time-domain samples. The first set of time-domain samples and the second set of time-domain samples are reordered to produce an output set of time-domain samples.

Abstract: Disclosed herein is a method for automatic gain control based on signal spectrum sensing. Spectral sensing techniques may be employed to detect the presence or absence of interference and also determine a frequency location of the interference and power level estimates of a desired signal. The method includes running an algorithm to measure the energy periodically to track the changes as blockers that were not prominent while experiencing deep fade and those that will affect performance when it is out of the deep fade. The method enables predicting a level of degradation for various front-end settings and enables selection of an optimum setting. In an embodiment, the spectral sensing may be performed either in analog domain using narrowband tunable filters. In an embodiment, the spectral sensing may be performed digitally using Fast fourier transform (FFT), Goertzel algorithm, or power detection techniques.

Abstract: Disclosed is a receiver for enhancing estimation of a channel of a received signal. The receiver is being configured to (i) process at least one of (a) power control commands to obtain a pattern of processed power control commands or (b) phase estimation to obtain a pattern of processed phase estimation; (ii) match the pattern of at least one of (a) processed power control commands, or (b) processed phase estimation to a pattern corresponding to one or more channels; (iii) determine a type of channel of the one or more channels based on the matched pattern of at least one of (a) said processed power control commands, or (b) said processed phase estimation, (iv) determine filtering parameters based on a type of channel that is determined and (v) enhance estimation of the channel based on the filtering parameters associated with the type of channel that is determined.

Abstract: Enhancing search capacity of Global Navigation Satellite System (GNSS) receivers. A method for searching satellite signals in a receiver includes performing a plurality of searches sequentially. The method also includes storing a result from each search of the plurality of searches in a consecutive section of a memory. Further, the method includes detecting free sections in the memory. The method also includes concatenating the free sections in the memory to yield a concatenated free section. Moreover, the method includes allocating the concatenated free section for performing an additional search.