Patents by Inventor Aravind K. Navada

Aravind K. Navada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Data communication interface for processing data in low power systems
    Patent number: 10482045
    Abstract: Improvements over existing data collection interfaces disclosed herein include, among other things, additional logic blocks (and associated timers, state machines, and registers) to off-load data collection and data processing prior to waking a microprocessor from a sleep mode. For example, an improved data collection interface collects a predetermined number of sensor values from a sensor while maintaining active a single communication session with the sensor over a pin of the interface. The microprocessor remains in the sleep mode for an entire duration of the single communication session. The data collection interface can reduce the likelihood of false starts of the microprocessor by using the logic blocks to verify that data meet preconditions prior to interrupting the microprocessor. The data collection interface can reduce the overall power consumption of a chip in which the microprocessor is integrated by a factor of at least about 2× (i.e., 50% reduction in power consumption).
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: November 19, 2019
    Assignee: ANALOG DEVICES GLOBAL UNLIMITED COMPANY
    Inventors: Mohamed Farook Basheer Ahamed, Michael Martin McCarthy, Aravind K. Navada
  • DATA COMMUNICATION INTERFACE FOR PROCESSING DATA IN LOW POWER SYSTEMS
    Publication number: 20170235692
    Abstract: Improvements over existing data collection interfaces disclosed herein include, among other things, additional logic blocks (and associated timers, state machines, and registers) to off-load data collection and data processing prior to waking a microprocessor from a sleep mode. For example, an improved data collection interface collects a predetermined number of sensor values from a sensor while maintaining active a single communication session with the sensor over a pin of the interface. The microprocessor remains in the sleep mode for an entire duration of the single communication session. The data collection interface can reduce the likelihood of false starts of the microprocessor by using the logic blocks to verify that data meet preconditions prior to interrupting the microprocessor. The data collection interface can reduce the overall power consumption of a chip in which the microprocessor is integrated by a factor of at least about 2× (i.e., 50% reduction in power consumption).
    Type: Application
    Filed: June 20, 2016
    Publication date: August 17, 2017
    Applicant: ANALOG DEVICES GLOBAL
    Inventors: MOHAMED FAROOK BASHEER AHAMED, MICHAEL MARTIN MCCARTHY, ARAVIND K. NAVADA
  • Efficient scheduling of read and write transactions in dynamic memory controllers
    Patent number: 8886844
    Abstract: Data-transfer transactions in the read and write directions may be balanced by taking snapshots of the transactions stored in a buffer, and executing transactions in the same direction back-to-back for each snapshot.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: November 11, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Krishna S. A. Jandhyam, Aravind K. Navada
  • Efficient scheduling of transactions from multiple masters
    Patent number: 8880745
    Abstract: Data-transfer transactions from multiple masters may be balanced by taking snapshots of the transactions stored in a buffer, and executing transactions from each master back-to-back.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: November 4, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Krishna S. A. Jandhyam, Aravind K. Navada
  • Efficient Scheduling of Read and Write Transactions in Dynamic Memory Controllers
    Publication number: 20140101339
    Abstract: Data-transfer transactions in the read and write directions may be balanced by taking snapshots of the transactions stored in a buffer, and executing transactions in the same direction back-to-back for each snapshot.
    Type: Application
    Filed: October 5, 2012
    Publication date: April 10, 2014
    Applicant: ANALOG DEVICES, INC.
    Inventors: Krishna S.A. Jandhyam, Aravind K. Navada
  • Efficient Scheduling of Transactions from Multiple Masters
    Publication number: 20140101340
    Abstract: Data-transfer transactions from multiple masters may be balanced by taking snapshots of the transactions stored in a buffer, and executing transactions from each master back-to-back.
    Type: Application
    Filed: October 5, 2012
    Publication date: April 10, 2014
    Inventors: Krishna S.A. Jandhyam, Aravind K. Navada