Abstract: A method for simulating a power consumption associated with a circuit. Once a netlist describing the circuit and an input stimulus for the netlist are obtained, the netlist is partitioned into multiple circuit blocks. Circuit logic models (CLMs) implemented in a hardware description language (HDL) are then obtained for the multiple circuit blocks and a logic netlist is generated from the multiple CLMs. A power vector for a CLM corresponding to a circuit block is calculated using a logic simulator inputting the logic netlist and the input stimulus. Further, a power consumption value is calculated for the circuit block using a circuit simulator and the power vector. The power consumption associated with the circuit is calculated based on the power consumption values for various circuit blocks.

Abstract: A method for simulating a power consumption associated with a circuit. The method includes: obtaining a netlist describing the circuit and an input stimulus for the netlist; partitioning the netlist into multiple circuit blocks; obtaining multiple circuit logic models (CLMs) implemented in a hardware description language (HDL) for the multiple circuit blocks; generating a logic netlist from the multiple CLMs; calculating, using a logic simulator inputting the logic netlist and the input stimulus, a power vector for a CLM corresponding to a first circuit block; calculating, using a circuit simulator and the power vector, a first power consumption value for the first circuit block; and calculating the power consumption associated with the circuit based on the first power consumption value.

Abstract: Embodiments of the present invention provide a method and system for clock-gating a circuit. During operation, the system receives a description of a circuit that includes clocked memory elements, some of which are clock-gated. Next, the system identifies a sender memory element by identifying a sender path from an output of the sender memory element to a data input for a seed memory element. Then, the system identifies an enable-generating memory element by identifying an enable-signal path from an output of the enable-generating memory element to an enable signal which is used to gate a clock signal input for the seed memory element. Next, the system provides clock-gating for the sender memory element by generating an enable signal using a data input for the enable-generating memory element. Finally, the system gates a clock signal for the sender memory element using this generated enable signal.

Abstract: A method and system of merging gated-clock domains in a semiconductor design includes producing, for each subset of clock gating functions in an initial set of clock gating functions, a set of quantified functions produced by existentially quantifying each clock gating function in the subset over a set of variables that are not part of the support sets of the other clock gating functions of the subset. If the set of quantified functions are equal, selecting one as a super clock gating function and adding it to the set of super clock gating functions. The set of super clock gating functions are sorted according to a criterion and the best is selected and added to the set of final clock gating functions. The remaining super clock gating functions are modified to prevent flip-flops gated by the selected super clock gating function from being gated by remaining super clock gating functions.

Abstract: Embodiments of the present invention provide a method and system for clock-gating a circuit. During operation, the system receives a circuit which includes a plurality of clocked memory elements. Next, the system identifies a feedback path from an output of a clocked memory element to an input of the clocked memory element, wherein the feedback path passes through intervening combinational logic, but does not pass through other clocked memory elements in the circuit. Then, the system gates a clock signal to the clocked memory element so that the clock signal is disabled when the feedback path causes a value which appears at the output of the clocked memory element to be appear at the input of the clocked memory element.

Abstract: Embodiments of the present invention provide a method and system for clock-gating a circuit. During operation, the system receives a description of a circuit that includes clocked memory elements, some of which are clock-gated. Next, the system identifies a sender memory element by identifying a sender path from an output of the sender memory element to a data input for a seed memory element. Then, the system identifies an enable-generating memory element by identifying an enable-signal path from an output of the enable-generating memory element to an enable signal which is used to gate a clock signal input for the seed memory element. Next, the system provides clock-gating for the sender memory element by generating an enable signal using a data input for the enable-generating memory element. Finally, the system gates a clock signal for the sender memory element using this generated enable signal.

Abstract: A method and system of merging gated-clock domains in a semiconductor design includes producing, for each subset of clock gating functions in an initial set of clock gating functions, a set of quantified functions produced by existentially quantifying each clock gating function in the subset over a set of variables that are not part of the support sets of the other clock gating functions of the subset. If the set of quantified functions are equal, selecting one as a super clock gating function and adding it to the set of super clock gating functions. The set of super clock gating functions are sorted according to a criterion and the best is selected and added to the set of final clock gating functions. The remaining super clock gating functions are modified to prevent flip-flops gated by the selected super clock gating function from being gated by remaining super clock gating functions.

Abstract: Embodiments of the present invention provide a method and system for clock-gating a circuit. During operation, the system receives a circuit which includes a plurality of clocked memory elements. Next, the system identifies a feedback path from an output of a clocked memory element to an input of the clocked memory element, wherein the feedback path passes through intervening combinational logic, but does not pass through other clocked memory elements in the circuit. Then, the system gates a clock signal to the clocked memory element so that the clock signal is disabled when the feedback path causes a value which appears at the output of the clocked memory element to be appear at the input of the clocked memory element.