Abstract: A forksheet FET device and processes for fabricating the same are provided. A semiconductor device includes a dielectric wall; a first semiconductor layer extending in a first direction perpendicular from a first side of the dielectric wall, the first semiconductor layer having a first end that is nearest to the dielectric wall; and a first gate electrode layer including a first gate extension that extends beyond the first end of the first semiconductor layer nearer to the first side of the dielectric wall.

Abstract: A device includes a two transistor zero capacitor gain cell that is back end of line compatible and includes a write transistor and a read transistor that is electrically connected to the write transistor. The write transistor includes an oxide semiconductor channel and the read transistor includes a polysilicon channel.

Abstract: Disclosed herein are methods, devices and systems including a substrate, a transistor channel on the substrate and extending in direction parallel to the substrate, a first electrode extending in a direction orthogonal to the substrate and coupled to the transistor channel, a second electrode coupled to the transistor channel and extending in a direction orthogonal to the substrate and parallel to the first electrode, and a first epitaxial structure arranged between the transistor channel and the first electrode. The first epitaxial structure may share a common crystalline orientation with the transistor channel, and may separate a surface of the first electrode and a surface of the transistor channel in a direction parallel to the substrate by a distance varying along the length of the first electrode.

Abstract: A method, apparatus, and system are provided. The method includes the steps of depositing a dummy stressor into a source and drain (S/D) region between a first sidewall and a second sidewall of a transistor before an epitaxial (EPI) layer is deposited into the S/D region; removing a polysilicon fin between the second sidewall and a third sidewall of the transistor to expose an initial stack; removing the dummy stressor from the S/D region; and depositing the EPI layer into the S/D region.

Abstract: A method of manufacturing a three-dimensional field-effect transistor including an upper field-effect transistor stacked on a lower field-effect transistor. The method includes epitaxially growing source/drain regions of the lower field-effect effect transistor, growing a sacrificial layer on an upper surface of the source/drain regions, and epitaxially growing source/drain regions of the upper field-effect transistor on the sacrificial layer. The sacrificial layer is a seed layer for the source/drain regions of the upper field-effect transistor. The method also includes selectively etching the sacrificial layer to form a gap between the source/drain regions of the lower field-effect transistor and the source/drain regions of the upper field-effect transistor, and depositing an oxide layer in the gap.

Abstract: Provided are systems, methods, and apparatuses for applying stress in transistors. In one or more examples, the systems, devices, and methods include depositing an epitaxial film on a surface between a first sidewall and a second sidewall of the transistor; depositing a dielectric over the epitaxial film and on the surface between the first sidewall and the second sidewall to increase stress in a silicon channel of the transistor; removing a polysilicon fin between the second sidewall and a third sidewall; and depositing a first metal between the second sidewall and the third sidewall based on removing the polysilicon fin.

Abstract: According to one or more embodiments of the present disclosure, a semiconductor device is described. The semiconductor device may include a substrate, a channel portion on the substrate between a source region and a drain region, and a gate on the channel. The channel portion may include a first portion extending in a first direction and at least one second portion protruding from the first portion in a second direction crossing the first portion.

Abstract: A field-effect transistor includes a substrate, a channel on the substrate including a stem including silicon extending in a vertical direction from the substrate and a number of prongs including silicon extending in a horizontal direction from the stem and spaced apart from each other along the vertical direction, an interfacial layer surrounding the stem and the prongs of the channel, a dielectric layer on the interfacial layer and surrounding the stem and the prongs of the channel, and a metal gate on the dielectric layer and surrounding the stem and the prongs of the channel.

Abstract: A method for manufacturing a semiconductor device according to one or more embodiments may include growing a first epitaxy layer at a first side and a second side of a stack of gates and channels, applying a sacrificial layer on the first epitaxy layer, growing a second epitaxy layer on the sacrificial layer, removing the sacrificial layer, and depositing a metal layer on the first epitaxy layer and the second epitaxy layer at the first side of the stack of gates and channels.