Patents by Inventor Arbind Kumar

Arbind Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230005153
    Abstract: Embodiments of the present disclosure are related to providing a method and device processing a first set of volumetric image data comprising cross-sectional images of a myocardium and displaying a second set of volumetric image data of the myocardium. A curved plane to rectangular plane transformation of cross-sectional images of myocardium of human heart is proposed. After the transformation, a combined and reconstructed set of myocardium images are superimposed with a modified Bull's Eye View (BEV) map and corresponding parameters indicating extent of fibrosis to obtain a second set of volumetric image data of myocardium. In addition to quantifying and displaying the extent of fibrosis, the proposed solution preserves neighborhood and adjacency criteria of abnormal tissues of myocardium walls of human heart.
    Type: Application
    Filed: December 4, 2020
    Publication date: January 5, 2023
    Inventor: Arbind Kumar GUPTA
  • Publication number: 20170193192
    Abstract: Methods and systems are provided for assessing compatibility between forms of medication in a clinical setting. Generally, a medical order for a patient is received, which specifies a task with an initial form of a medical agent to be administered to the patient. When a clinician attempts to administer the medical agent to the patient, a current form of the medical agent is received from a scanning device, for example. As such, it may be determined whether the current form is compatible with the initial form. When it is determined that the current form is not compatible with the initial form, an error may be generated and issued in an effort to prevent administration of the current form to the patient.
    Type: Application
    Filed: March 3, 2016
    Publication date: July 6, 2017
    Inventors: ARBIND KUMAR CHOUBEY, BRETT AARON BARKER, DEEPAK GUPTA, LISA MARIE SMITH, LISA ANN WIEDEMANN, PIYUSH KUMAR, SCOTT ALAN JULIUS
  • Publication number: 20160125109
    Abstract: A method for operating a data processing system to simulate a circuit that includes a plurality of circuit devices connected by interconnects. A layout description of the circuit is provided in which the devices are connected by interconnects. Each interconnect is associated with a line definition that includes a physical description of an interconnect between two of the circuit devices and a simulation model to be used in simulating the interconnect during simulations of the circuit. The line definitions are user selectable from a list of available line definitions. A circuit netlist is generated by reading physical interconnects from the layout. At least one of the interconnects is replaced by a plurality of transmission line devices, each device being associated with the simulation model included in the line definition. The circuit is then simulated using the netlist.
    Type: Application
    Filed: November 3, 2014
    Publication date: May 5, 2016
    Applicant: Keysight Technologies, Inc.
    Inventors: Krishna Kumar Banka, Prantik Sarkar, Harald Devos, Peter Niday, John Robert Kenneth Lefebvre, II, Arbind Kumar, Atul Dubey
  • Patent number: 9317638
    Abstract: A method for operating a data processing system to simulate a circuit that includes a plurality of circuit devices connected by interconnects. A layout description of the circuit is provided in which the devices are connected by interconnects. Each interconnect is associated with a line definition that includes a physical description of an interconnect between two of the circuit devices and a simulation model to be used in simulating the interconnect during simulations of the circuit. The line definitions are user selectable from a list of available line definitions. A circuit netlist is generated by reading physical interconnects from the layout. At least one of the interconnects is replaced by a plurality of transmission line devices, each device being associated with the simulation model included in the line definition. The circuit is then simulated using the netlist.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: April 19, 2016
    Assignee: Keysight Technologies, Inc.
    Inventors: Krishna Kumar Banka, Prantik Sarkar, Harald Devos, Peter Niday, John Robert Kenneth Lefebvre, II, Arbind Kumar, Atul Dubey
  • Patent number: 8584077
    Abstract: A method for operating a computer system to generate a layout of a device and a computer-readable medium containing instructions that cause a computer system to carry out that method are disclosed. The computer system has a display that includes a display area. The computer system provides a list of objects and creates user selected objects from the list for inclusion in the display area. The computer assigns one of a plurality of operating modes for each connectivity object in the layout. The computer generates a Net assignment for each connectivity object that is not forced to have a specific Net assignment and for which automatic assignment of a Net is allowed. The computer generated assignment depends on the operating mode associated with that connectivity object. The operating mode of at least one of the connectivity objects can be altered by input from a user of said computer system.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: November 12, 2013
    Assignee: Agilent Technologies, Inc.
    Inventors: Arbind Kumar, John Robert Lefebvre, II, Krishna Kumar Banka, Peter Niday
  • Patent number: 8327315
    Abstract: According to various embodiments of the invention, a system and method for editing process rules for circuit design through a graphical editor is provided. In some embodiments, the graphical editor is a circuit design tool that provides the user of the tool, such as a circuit designer or process engineer, the ability to visualize, modify, create, or remove process rules through a graphical user interface (“GUI”). These process rules, also known as constraints or circuit design constraints, relate to the layout of circuits and is grouped into constraint groups (also known as “circuit design constraint groups”) that can be associated to specific circuit design objects.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: December 4, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Sandipan Ghosh, Hitesh Marwah, Pawan Fangaria, Arbind Kumar