Patents by Inventor Arch D. Robison

Arch D. Robison has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7165245
    Abstract: The present invention is a method and system to reduce storage in a inter-procedural analysis solver. In one embodiment, local graphs are pruned. The local graphs represent local problems, which correspond to separately compilable components in a software program. Each of the local graphs has edges and vertices. Each edge has a transfer function. Each vertex has a value. Values of the local graph form a lattice under a partial ordering.
    Type: Grant
    Filed: April 27, 2001
    Date of Patent: January 16, 2007
    Assignee: Intel Corporation
    Inventor: Arch D. Robison
  • Patent number: 7120904
    Abstract: A method for analyzing and optimizing programs that operate on a data structure where the state of the data structure must be valid at certain program points. The program is represented as a control-flow graph. The method decomposes the state of the data structure into components, and applies partial redundancy elimination to place instructions that set the state of the data structure, with a variation that permits speculative placement. Application extends to manipulating a stack that keeps track of what to do should an exception arise during execution. In this context, a control-flow representation of contingencies is converted into placement of instructions that manipulate the stack.
    Type: Grant
    Filed: April 19, 2000
    Date of Patent: October 10, 2006
    Assignee: Intel Corporation
    Inventor: Arch D. Robison
  • Publication number: 20040243982
    Abstract: A method for analyzing and optimizing programs that operate on a data structure where the state of the data structure must be valid at certain program points. The program is represented as a control-flow graph. The method decomposes the state of the data structure into components, and applies partial redundancy elimination to place instructions that set the state of the data structure, with a variation that permits speculative placement. Application extends to manipulating a stack that keeps track of what to do should an exception arise during execution. In this context, a control-flow representation of contingencies is converted into placement of instructions that manipulate the stack.
    Type: Application
    Filed: October 24, 2003
    Publication date: December 2, 2004
    Inventor: Arch D. Robison
  • Patent number: 6820253
    Abstract: A method and system for interprocedural analysis with separate compilation is disclosed. In one embodiment, the method is applied to a software program having a plurality of separately compilable components. The method performs analyzing each component separately to create a plurality of local problems for each component and merging the local problems to create a global problem.
    Type: Grant
    Filed: September 27, 2000
    Date of Patent: November 16, 2004
    Assignee: Intel Corporation
    Inventor: Arch D. Robison
  • Publication number: 20040128659
    Abstract: An arrangement is provided for eliminating partial redundancy. Original code is processed to perform run-time behavior preserving redundancy elimination. Partial redundancy is removed in a manner so that the run-time behavior of the original code is preserved.
    Type: Application
    Filed: December 31, 2002
    Publication date: July 1, 2004
    Applicant: Intel Corporation
    Inventor: Arch D. Robison
  • Publication number: 20030131344
    Abstract: A system and method to reduce the size of executable code in a processing system are described. Multiple subgraph structures are identified within a graph structure constructed for multiple executable instructions in a program. Unifiable variables that are not simultaneously used in the executable instructions are identified within each subgraph structure. Finally, one or more unifiable instructions from a tine of a corresponding subgraph structure are transferred to a handle of the corresponding subgraph structure, each unifiable instruction containing one or more unifiable variables.
    Type: Application
    Filed: January 3, 2002
    Publication date: July 10, 2003
    Inventor: Arch D. Robison
  • Publication number: 20030074655
    Abstract: In an embodiment, a method includes receiving a code segment having a plurality of instructions. The code segment includes an outer scope and a number of inner scopes. Additionally, the plurality of instructions comprise a number of pointers, wherein at least one of the number of pointers is restricted. The method also includes determining, within one of the number of inner scopes, whether at least two pointers of the number of pointers are aliases.
    Type: Application
    Filed: September 27, 2001
    Publication date: April 17, 2003
    Inventor: Arch D. Robison
  • Publication number: 20020162096
    Abstract: The present invention is a method and system to reduce storage in a inter-procedural analysis solver. In one embodiment, local graphs are pruned. The local graphs represent local problems, which correspond to separately compilable components in a software program. Each of the local graphs has edges and vertices. Each edge has a transfer function. Each vertex has a value. Values of the local graph form a lattice under a partial ordering.
    Type: Application
    Filed: April 27, 2001
    Publication date: October 31, 2002
    Inventor: Arch D. Robison
  • Patent number: 6370685
    Abstract: A method for analyzing and optimizing programs that contain pointers or aggregates or both, such as found in the languages C, C++, FORTRAN-90, Ada, and Java is disclosed. The program is represented as a control flow graph. The method applies to storage locations (lvalues) computed by instructions in a program. The data flow analysis distinguishes when a definition might reach a use, and if so, whether the expression defining the address of the defined lvalue may have changed. The method ignores changes to the addressing expression where a definition does not reach. The lattice values and functions employed by the analysis are compactly represented as packed bit vectors, and operated upon in a parallel bitwise fashion. Despite the generality of definitions that define lvalues specified by expressions, the present invention computes the reachability of the definitions with a single data-flow framework that requires only one fixed-point solution per data-flow problem.
    Type: Grant
    Filed: January 6, 1999
    Date of Patent: April 9, 2002
    Assignee: Intel Corporation
    Inventor: Arch D. Robison
  • Patent number: 5805894
    Abstract: A method of analyzing and optimizing programs by predicting branches and redirecting control flow. A program to be analyzed and optimized is inspected to find branches that might be predictable. A set of assertions is generated, analyzed by a dataflow solver and then used to predict the effects of branches. Control flow in the program is redirected to skip over predictable branches. The dataflow solver is capable of analyzing assertions involving lvalues such as variables, pointer expressions, or components of aggregate lvalues.
    Type: Grant
    Filed: March 6, 1996
    Date of Patent: September 8, 1998
    Assignee: Kuck & Associates, Inc.
    Inventor: Arch D. Robison
  • Patent number: 5790866
    Abstract: A method for analyzing and optimizing programs that contain pointers and/or aggregates, such as found in the languages C, C++, FORTRAN-90, and Ada. The method applies to storage locations (lvalues) and values (rvalues) computed by expressions.Data-flow analysis is performed on two levels. The bottom level determines when an rvalue computed at one point in a program is the same if recomputed at a later point in the program. The top level computes reaching definitions, based upon information provided by the bottom level. Each destination lvalue may be designated by an arbitrary rvalue (pointer-expression). Splitting of data-flow analysis into two levels allows computation of reaching definitions that involve assignments to lvalues with designating rvalues that are arbitrary expressions.Furthermore, for aggregate lvalues, which themselves may contain components that are pointers to other aggregates, data-flow analysis is done on a component-by-component basis.
    Type: Grant
    Filed: February 13, 1995
    Date of Patent: August 4, 1998
    Assignee: Kuck and Associates, Inc.
    Inventor: Arch D. Robison
  • Patent number: 5710927
    Abstract: A method for analyzing and optimizing programs that define and use aggregate data structures. A program to be analyzed and optimized is inspected to find definitions and uses of lvalues, which are regions of memory. The lvalues may be denoted by program variables, pointer expressions, or components of aggregate lvalues. A data-flow solver determines where definitions of lvalues reach uses. A set of "least general unifiers" are computed for the definitions and uses. A replacement variable is created for each least general unifier that is determined to be replaceable. Each reference to an lvalue that corresponds to a replaceable least general unifier is replaced by a reference to the corresponding replacement variable or a component thereof. The method is applicable even in the presence of potential aliasing.
    Type: Grant
    Filed: June 14, 1995
    Date of Patent: January 20, 1998
    Assignee: Kuck & Associates, Inc.
    Inventor: Arch D. Robison